fmul

Floating-Point Multiply (Half-Precision)

FMUL <Vd>.8H, <Vn>.8H, <Vm>.8H

Multiplies two half-precision floating-point vectors.

Details

Multiplies half-precision floating-point elements in Vn by corresponding elements in Vm, writing results to Vd. Operates on 8 half-precision (16-bit) floating-point values packed in 128-bit vectors. No condition flags are affected; floating-point exceptions follow FPCR rounding and exception control settings. Requires FEAT_FP16 extension; AArch64-only.

Pseudocode Operation

for i = 0 to 7
  Vd[i*16 +: 16] ← FP16_Mul(Vn[i*16 +: 16], Vm[i*16 +: 16])

Example

FMUL v0.4s.8H, v1.4s.8H, v2.4s.8H

Encoding

Binary Layout
0
Q
1
01110
0
10
Rm
00
011
1
Rn
Rd
 
Format NEON FP16
Opcode 0x2E401C00
Extension FEAT_FP16 (NEON)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F009000 FMUL <Hd>, <Hn>, <Vm>.H[<index>] A64 01 | 0 | 11111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x5F809000 FMUL <V><d>, <V><n>, <Vm>.<Ts>[<index>] A64 01 | 0 | 111111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F009000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.H[<index>] A64 0 | Q | 0 | 01111 | 00 | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x0F809000 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<Ts>[<index>] A64 0 | Q | 0 | 011111 | sz | L | M | Rm | 1001 | H | 0 | Rn | Rd
0x2E401C00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | 0 | 10 | Rm | 00 | 011 | 1 | Rn | Rd
0x2E20DC00 FMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 011100 | sz | 1 | Rm | 11011 | 1 | Rn | Rd
0x1EE00800 FMUL <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E200800 FMUL <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 0 | 00010 | Rn | Rd
0x1E600800 FMUL <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 0 | 00010 | Rn | Rd
0x651A8000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 01 | 0 | 100 | Pg | 0000 | i1 | Zdn
0x65028000 FMUL <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 001 | 0 | 100 | Pg | Zm | Zdn
0x65000800 FMUL <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 01 | 0 | Zn | Zd
0x64202000 FMUL <Zd>.H, <Zn>.H, <Zm>.H[<imm>] A64 01100100 | 0 | i3h | 1 | i3l | Zm | 0010 | 0 | 0 | Zn | Zd
0x64A02000 FMUL <Zd>.S, <Zn>.S, <Zm>.S[<imm>] A64 01100100 | 1 | 0 | 1 | i2 | Zm | 0010 | 0 | 0 | Zn | Zd

Description

Floating-point Multiply (vector). This instruction multiplies corresponding floating-point values in the vectors in the two source SIMD&FP registers, places the result in a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPMul(element1, element2, FPCR);

V[d, datasize] = result;