eorv

SVE Bitwise EOR Reduction

EORV <Vd>, <Pg>, <Zn>.<T>

XORs all active elements into a scalar.

Pseudocode Operation

bits(smax(8*datasize,32)) result = Vd<smax(8*datasize,32)-1:0>;
for i = 0 to (VL/esize)-1
    if Pg[i]
        result = result XOR Zn[i*esize+esize-1:i*esize]
Vd = result<smax(8*datasize,32)-1:0>;

Example

EORV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout

00000100

31:24

size

23:22

0110

21:18

0

17

1

16

001

15:13

Pg

12:10

Zn

9:5

Vd

4:0

 

Format SVE Reduction

Opcode 0x04192000

Extension SVE

Operands

• Vd
  Dest Scalar
• Pg
  Mask
• Zn
  Vector

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x04192000	EORV <V><d>, <Pg>, <Zn>.<T>		A64		00000100 | size | 0110 | 0 | 1 | 001 | Pg | Zn | Vd

Description

Bitwise exclusive OR horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(esize) result = Zeros(esize);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        result = result EOR Elem[operand, e, esize];

V[d, esize] = result;