eorv

SVE Bitwise EOR Reduction

EORV <Vd>, <Pg>, <Zn>.<T>

XORs all active elements into a scalar.

Details

SVE bitwise XOR reduction that combines all active predicated elements of a scalable vector into a scalar result. The operation iteratively XORs each active element into the destination scalar register. No condition flags are affected by this instruction. This is an AArch64-only SVE instruction.

Pseudocode Operation

bits(smax(8*datasize,32)) result = Vd<smax(8*datasize,32)-1:0>;
for i = 0 to (VL/esize)-1
    if Pg[i]
        result = result XOR Zn[i*esize+esize-1:i*esize]
Vd = result<smax(8*datasize,32)-1:0>;

Example

EORV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout
00000100
size
0110
0
1
001
Pg
Zn
Vd
 
Format SVE Reduction
Opcode 0x04192000
Extension SVE

Operands

  • Vd
    Dest Scalar
  • Pg
    Mask
  • Zn
    Vector

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x04192000 EORV <V><d>, <Pg>, <Zn>.<T> A64 00000100 | size | 0110 | 0 | 1 | 001 | Pg | Zn | Vd

Description

Bitwise exclusive OR horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Inactive elements in the source vector are treated as zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(esize) result = Zeros(esize);

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        result = result EOR Elem[operand, e, esize];

V[d, esize] = result;