orn

Vector Bitwise OR NOT

ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

ORs Vd with NOT of Vm.

Details

The Vector Bitwise OR NOT instruction oRs Vd with NOT of Vm.

Pseudocode Operation

Vd ← Vn OR NOT Vm

Example

ORN v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
001110
11
1
Rm
0001
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0EE01C00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register