orn
Vector Bitwise OR NOT
ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T>
ORs Vd with NOT of Vm.
Details
Performs a bitwise OR NOT operation on SIMD vector elements: each bit in Vd is set to (Vn | ~Vm). This is a bitwise logical operation that operates independently on each bit across all lanes. No condition flags are affected. Executes in AArch64 state with NEON extension; operates on both 64-bit (Q=0) and 128-bit (Q=1) vector registers.
Pseudocode Operation
for i = 0 to (datasize / 8) - 1
Vd[i*8 +: 8] ← Vn[i*8 +: 8] | ~Vm[i*8 +: 8]
Example
ORN v0.4s.T, v1.4s.T, v2.4s.T
Encoding
Binary Layout
0
Q
0
01110
11
1
Rm
00011
1
Rn
Rd
Operands
-
Vd
Destination SIMD/FP vector register -
Vn
First source SIMD/FP vector register -
Vm
Second source SIMD/FP vector register
Reference (Arm A64 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0EE01C00 | ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> | A64 | 0 | Q | 0 | 01110 | 11 | 1 | Rm | 00011 | 1 | Rn | Rd | ||
| 0x2A200000 | ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>} | A64 | 0 | 01 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd | ||
| 0xAA200000 | ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>} | A64 | 1 | 01 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd | ||
| 0x05000000 | ORN <Zdn>.<T>, <Zdn>.<T>, #<const> | A64 | 00000101 | 0 | 0 | 0000 | imm13 | Zdn | ||
| 0x25804010 | ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B | A64 | 00100101 | 1 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 1 | Pd |
Description
Bitwise inclusive OR NOT (vector). This instruction performs a bitwise OR NOT between the two source SIMD&FP registers, and writes the result to the destination SIMD&FP register.
Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
CheckFPAdvSIMDEnabled64(); bits(datasize) operand1 = V[n, datasize]; bits(datasize) operand2 = V[m, datasize]; bits(datasize) result; operand2 = NOT(operand2); result = operand1 OR operand2; V[d, datasize] = result;