whilehs

SVE While Higher or Same (Unsigned)

WHILEHS <Pd>.<T>, <Xn>, <Xm>

Generates predicate for unsigned loop (while Xn >= Xm).

Details

Generates a predicate where each element is true if the corresponding loop counter (Xn + element_index) is greater than or equal to Xm (unsigned comparison). The output predicate Pd has element width determined by <T>. This is an AArch64-only SVE instruction; all condition flags are unaffected.

Pseudocode Operation

element_size ← size_in_bytes(<T>)
for i = 0 to VL/element_size-1
  if (Xn + i) >= Xm then
    Pd[i] ← 1
  else
    Pd[i] ← 0
  endif
endfor

Example

WHILEHS p0.T, x1, x2

Encoding

Binary Layout
00100101
size
1
Rm
000
sf
1
0
Rn
0
Pd
 
Format SVE Compare
Opcode 0x25200800
Extension SVE

Operands

  • Pd
    Destination predicate register (SVE)
  • Xn
    Start
  • Xm
    Limit

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x25200800 WHILEHS <Pd>.<T>, <R><n>, <R><m> A64 00100101 | size | 1 | Rm | 000 | sf | 1 | 0 | Rn | 0 | Pd
0x25204810 WHILEHS <PNd>.<T>, <Xn>, <Xm>, <vl> A64 00100101 | size | 1 | Rm | 01 | vl | 0 | 1 | 0 | Rn | 1 | 0 | PNd
0x25205810 WHILEHS { <Pd1>.<T>, <Pd2>.<T> }, <Xn>, <Xm> A64 00100101 | size | 1 | Rm | 0101 | 1 | 0 | Rn | 1 | Pd | 0

Description

Generate a predicate that starting from the highest numbered element is true while the decrementing value of the first, unsigned scalar operand is higher or same as the second scalar operand and false thereafter down to the lowest numbered element. If the second scalar operand is equal to the minimum unsigned integer value then a condition which includes an equality test can never fail and the result will be an all-true predicate. The full width of the scalar operands is significant for the purposes of comparison, and the full width first operand is decremented by one for each destination predicate element, irrespective of the predicate result element size. The first general-purpose source register is not itself updated. The predicate result is placed in the predicate destination register. Sets the First (N), None (Z), !Last (C) condition flags based on the predicate result, and the V flag to zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = Ones(PL);
bits(rsize) operand1 = X[n, rsize];
bits(rsize) operand2 = X[m, rsize];
bits(PL) result;
boolean last = TRUE;
constant integer psize = esize DIV 8;

for e = elements-1 downto 0
    boolean cond;
    case op of
        when Cmp_GT cond = (Int(operand1, unsigned) >  Int(operand2, unsigned));
        when Cmp_GE cond = (Int(operand1, unsigned) >= Int(operand2, unsigned));

    last = last && cond;
    bit pbit = if last then '1' else '0';
    Elem[result, e, psize] = ZeroExtend(pbit, psize);
    operand1 = operand1 - 1;

PSTATE.<N,Z,C,V> = PredTest(mask, result, esize);
P[d, PL] = result;