orr

Bitwise OR (Immediate)

ORR <Wd|Wsp>, <Wn>, #<imm>

ORs register with logical immediate.

Details

Bitwise OR with logical immediate. Performs bitwise OR between Wn and a 32-bit bitmask immediate, storing the result in Wd. The immediate is expanded using the logical immediate encoding (N:immr:imms). Sets the Z flag if the result is zero; N, C, V flags are unaffected. AArch64-only instruction.

Pseudocode Operation

imm32 ← LogicalImmediate(N, immr, imms, 32)
Wd ← Wn | imm32
Z ← (Wd == 0)

Example

ORR Wd, w1, #16

Encoding

Binary Layout
0
01
100100
0
immr
imms
Rn
Rd
 
Format Logical (Immediate)
Opcode 0x32000000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • imm
    Imm

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0F009400 ORR <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0F001400 ORR <Vd>.<T>, #<imm8>{, LSL #<amount>} A64 0 | Q | 0 | 0111100000 | a | b | c | cmode | 0 | 1 | d | e | f | g | h | Rd
0x0EA01C00 ORR <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 10 | 1 | Rm | 00011 | 1 | Rn | Rd
0x32000000 ORR <Wd|WSP>, <Wn>, #<imm> A64 0 | 01 | 100100 | 0 | immr | imms | Rn | Rd
0xB2000000 ORR <Xd|SP>, <Xn>, #<imm> A64 1 | 01 | 100100 | N | immr | imms | Rn | Rd
0x2A000000 ORR <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 01 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0xAA000000 ORR <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 01 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25804000 ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 1 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd
0x04180000 ORR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 00 | 0 | 000 | Pg | Zm | Zdn
0x05000000 ORR <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 0 | 0 | 0000 | imm13 | Zdn
0x04603000 ORR <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 0 | 1 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate register value, and writes the result to the destination register.

Operation

bits(datasize) result;
bits(datasize) operand1 = X[n, datasize];

result = operand1 OR imm;
if d == 31 then
    SP[] = ZeroExtend(result, 64);
else
    X[d, datasize] = result;