pldw

Preload Data for Write (A32)

PLDW [<Rn>, #<imm>]

Hints memory system to bring data into cache for writing.

Details

Preloads data for write by hinting the memory system to allocate cache line(s) in an exclusive state at the address computed from the base register and 12-bit immediate offset. This is a hint instruction and does not cause exceptions on address translation or access faults. Condition flags and general-purpose registers are unaffected. This instruction executes in A32 (ARM) instruction set only.

Pseudocode Operation

address = Rn + imm12
// Hint to memory system to preload for exclusive access (write)
PreloadDataForWrite(address)

Example

PLDW [r1, #16]

Encoding

Binary Layout
1111010
1
U
0
01
Rn
1
1
1
1
imm12
 
Format Load/Store
Opcode 0xF510F000
Extension A32 (Base)

Operands

  • Rn
    First source / base general-purpose register
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF510F000 PLDW{<c>}{<q>} [<Rn> {, #{+/-}<imm>}] A32 1111010 | 1 | U | 0 | 01 | Rn | 1 | 1 | 1 | 1 | imm12
0xF8B0F000 PLDW{<c>}{<q>} [<Rn> {, #{+}<imm>}] T32 111110001 | 0 | 1 | 1 | Rn | 1111 | imm12
0xF830FC00 PLDW{<c>}{<q>} [<Rn> {, #-<imm>}] T32 111110000 | 0 | 1 | 1 | Rn | 1111 | 1100 | imm8
0xF710F000 PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> {, <shift> #<amount>}] A32 1111011 | 1 | U | 0 | 01 | Rn | 1 | 1 | 1 | 1 | imm5 | stype | 0 | Rm
0xF710F060 PLDW{<c>}{<q>} [<Rn>, {+/-}<Rm> , RRX] A32 1111011 | 1 | U | 0 | 01 | Rn | 1 | 1 | 1 | 1 | 00000 | 11 | 0 | Rm
0xF830F000 PLDW{<c>}{<q>} [<Rn>, {+}<Rm> {, LSL #<amount>}] T32 111110000 | 0 | 1 | 1 | Rn | 1111 | 000000 | imm2 | Rm

Description

Preload Data (immediate) signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as preloading the cache line containing the specified address into the data cache. The PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is implementation defined. For more information, see Preloading caches.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    address = if add then (R[n] + imm32) else (R[n] - imm32);
    if is_pldw then
        Hint_PreloadDataForWrite(address);
    else
        Hint_PreloadData(address);