strb

Store Register Byte (Register)

STRB <Wt>, [<Xn|SP>, <R><m> {, <extend> <amount>}]

Stores the low byte of a register using register offset.

Details

Stores the low byte (bits 7:0) of a 32-bit register to memory using register-based addressing with optional extension and shift of the offset register. Does not affect condition flags. AArch64-only; supports UXTW, UXTX, SXTW, SXTX extensions.

Pseudocode Operation

offset ← ExtendValue(Rm, option, S)
address ← Xn + offset
[address] ← Wt[7:0]

Example

STRB w3, [x1, Rm ]

Encoding

Binary Layout
00
111
0
00
00
1
Rm
option
S
10
Rn
Rt
 
Format Load/Store
Opcode 0x38200800
Extension Base

Operands

  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register
  • Rm
    Offset Reg

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x38000400 STRB <Wt>, [<Xn|SP>], #<simm> A64 00 | 111 | 0 | 00 | 00 | 0 | imm9 | 01 | Rn | Rt
0x38000C00 STRB <Wt>, [<Xn|SP>, #<simm>]! A64 00 | 111 | 0 | 00 | 00 | 0 | imm9 | 11 | Rn | Rt
0x39000000 STRB <Wt>, [<Xn|SP>{, #<pimm>}] A64 00 | 111 | 0 | 01 | 00 | imm12 | Rn | Rt
0x38200800 STRB <Wt>, [<Xn|SP>, (<Wm>|<Xm>), <extend> {<amount>}] A64 00 | 111 | 0 | 00 | 00 | 1 | Rm | option | S | 10 | Rn | Rt
0x38206800 STRB <Wt>, [<Xn|SP>, <Xm>{, LSL <amount>}] A64 00 | 111 | 0 | 00 | 00 | 1 | Rm | 011 | S | 10 | Rn | Rt

Description

Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a 32-bit register to the calculated address. For information about memory accesses, see Load/Store addressing modes. The instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an offset register value. The offset can be optionally shifted and extended.

Operation

bits(64) offset = ExtendReg(m, extend_type, 0, 64);
bits(64) address;
bits(8) data;

boolean privileged = PSTATE.EL != EL0;
AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, FALSE, privileged, TRUE);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data = X[t, 8];
Mem[address, 1, accdesc] = data;