pmul

Vector Polynomial Multiply

PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Performs polynomial multiplication over {0,1}.

Pseudocode Operation

for i = 0 to (128 >> (if Q then 0 else 1)) - 1 step 8:
  Vd[i +: 8] ← PolynomialMultiply(Vn[i +: 8], Vm[i +: 8]);

Example

PMUL v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout

0

31

Q

30

1

29

01110

28:24

size

23:22

1

21

Rm

20:16

10011

15:11

1

10

Rn

9:5

Rd

4:0

 

Format SIMD Three Register

Opcode 0x2E209C00

Extension NEON (SIMD)

Operands

• Vd
  Destination SIMD/FP vector register
• Vn
  First source SIMD/FP vector register
• Vm
  Second source SIMD/FP vector register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x2E209C00	PMUL <Vd>.<T>, <Vn>.<T>, <Vm>.<T>		A64		0 | Q | 1 | 01110 | size | 1 | Rm | 10011 | 1 | Rn | Rd
0x04206400	PMUL <Zd>.B, <Zn>.B, <Zm>.B		A64		00000100 | 0 | 0 | 1 | Zm | 0110 | 0 | 1 | Zn | Zd

Description

Polynomial Multiply. This instruction multiplies corresponding elements in the vectors of the two source SIMD&FP registers, places the results in a vector, and writes the vector to the destination SIMD&FP register. For information about multiplying polynomials see Polynomial arithmetic over {0, 1}. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
bits(esize) element1;
bits(esize) element2;
bits(esize) product;

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    if poly then
        product = PolynomialMult(element1, element2)<esize-1:0>;
    else
        product = (UInt(element1)*UInt(element2))<esize-1:0>;
    Elem[result, e, esize] = product;

V[d, datasize] = result;