vrshrn

Vector Rounding Shift Right Narrow

VRSHRN<c>.<dt> <Dd>, <Qm>, #<imm>

Shifts right, rounds, and narrows (2N -> N bits).

Details

Shifts each element of the 128-bit source register right by the immediate shift amount with rounding, then narrows the result from 2N bits to N bits (halving the element width), and stores into the 64-bit destination register. The high half of the shift result is kept. No condition flags are modified. This is a NEON instruction available in both A32 and T32 instruction sets.

Pseudocode Operation

for i = 0 to elements_in_Dd - 1
  shift_amount ← imm6
  if shift_amount > 2 × element_size then
    Dd[i] ← 0
  else
    value ← Qm[i]
    rounding_correction ← (1 << (shift_amount - 1))
    rounded ← (value + rounding_correction) >> shift_amount
    Dd[i] ← saturate(rounded, element_size / 2)
  endif
endfor

Example

VRSHRN.dt d0, q2, #16

Encoding

Binary Layout
111100111
D
11
size
10
Vd
0
0100
0
M
0
Vm
 
Format NEON Shift
Opcode 0xF3B20200
Extension NEON (SIMD)

Operands

  • Dd
    Dest Narrow
  • Qm
    Src Wide
  • imm
    Signed immediate value

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF2800850 VRSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm> A32 1111001 | 0 | 1 | D | imm6 | Vd | 1000 | 0 | 1 | M | 1 | Vm
0xEF800850 VRSHRN{<c>}{<q>}.I<size> <Dd>, <Qm>, #<imm> T32 111 | 0 | 11111 | D | imm6 | Vd | 1000 | 0 | 1 | M | 1 | Vm
0xF3B20200 VRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 A32 111100111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm
0xFFB20200 VRSHRN{<c>}{<q>}.<dt> <Dd>, <Qm>, #0 T32 111111111 | D | 11 | size | 10 | Vd | 0 | 0100 | 0 | M | 0 | Vm

Description

takes each element in a vector, right shifts them by an immediate value, and places the rounded results in the destination vector