umin

SVE Unsigned Minimum

UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Determines minimum unsigned value per element.

Details

SVE unsigned minimum: computes the element-wise minimum of two unsigned integer vectors (Zdn and Zm), writing results to Zdn under predicate mask control (Pg). Only elements where the predicate is active are updated; inactive elements retain their original values in Zdn. No condition flags are affected. This is an AArch64-only instruction requiring SVE support.

Pseudocode Operation

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← min_unsigned(Zdn[e], Zm[e])
  end if
end for

Example

UMIN z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
00000100
size
001
0
1
1
000
Pg
Zm
Zdn
 
Format SVE Integer Binary
Opcode 0x040B0000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2E206C00 UMIN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 1 | 01110 | size | 1 | Rm | 0110 | 1 | 1 | Rn | Rd
0x11CC0000 UMIN <Wd>, <Wn>, #<uimm> A64 0 | 0 | 0 | 1000111 | 0011 | imm8 | Rn | Rd
0x91CC0000 UMIN <Xd>, <Xn>, #<uimm> A64 1 | 0 | 0 | 1000111 | 0011 | imm8 | Rn | Rd
0xC120A021 UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101000 | 0000 | 1 | Zdn | 1
0xC120A821 UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101010 | 0000 | 1 | Zdn | 0 | 1
0xC120B021 UMIN { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } A64 11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 1 | Zdn | 1
0xC120B821 UMIN { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } A64 11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 1 | Zdn | 0 | 1
0x1AC06C00 UMIN <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 011011 | Rn | Rd
0x9AC06C00 UMIN <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 011011 | Rn | Rd
0x040B0000 UMIN <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 001 | 0 | 1 | 1 | 000 | Pg | Zm | Zdn
0x252BC000 UMIN <Zdn>.<T>, <Zdn>.<T>, #<imm> A64 00100101 | size | 101 | 01 | 1 | 11 | 0 | imm8 | Zdn

Description

Determine the unsigned minimum of active elements of the second source vector and corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    integer element1 = Int(Elem[operand1, e, esize], unsigned);
    integer element2 = Int(Elem[operand2, e, esize], unsigned);
    if ActivePredicateElement(mask, e, esize) then
        integer minimum = Min(element1, element2);
        Elem[result, e, esize] = minimum<esize-1:0>;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;