orn

Bitwise OR NOT

ORN <Wd>, <Wn>, <Wm> {, <shift> #<amount>}

ORs register with NOT of shifted register.

Details

Performs a bitwise OR between a register and the bitwise NOT of a second (optionally shifted) register, storing the result in the destination. All condition flags (N, Z, C, V) are updated based on the result; N and Z are set according to the result value, while C and V are cleared to zero. This is a 32-bit operation in the W-register form; a 64-bit X-register form also exists with identical semantics.

Pseudocode Operation

result ← Wn | ~(Wm << shift_amount)
Wd ← result
N ← result[31]
Z ← (result == 0)
C ← 0
V ← 0

Example

ORN w0, w1, w2

Encoding

Binary Layout
0
01
01010
shift
1
Rm
imm6
Rn
Rd
 
Format Logical (Register)
Opcode 0x2A200000
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    First source / base 32-bit integer register
  • Wm
    Second source / offset 32-bit integer register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EE01C00 ORN <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 11 | 1 | Rm | 00011 | 1 | Rn | Rd
0x2A200000 ORN <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 01 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0xAA200000 ORN <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 01 | 01010 | shift | 1 | Rm | imm6 | Rn | Rd
0x05000000 ORN <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 0 | 0 | 0000 | imm13 | Zdn
0x25804010 ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 1 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 1 | Pd

Description

Bitwise OR NOT (shifted register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = ShiftReg(m, shift_type, shift_amount, datasize);
bits(datasize) result;

operand2 = NOT(operand2);

result = operand1 OR operand2;
X[d, datasize] = result;