mvn

Move NOT (A32)

MVN{S}<c> <Rd>, <Operand2>

Moves bitwise inverse of value.

Pseudocode Operation

Rd ← ~Operand2
if S == 1 then
  N ← Rd[31]
  Z ← (Rd == 0)
  if Operand2_has_shift then C ← Operand2_carry_out
  V ← V

Example

MVN r0, r2

Encoding

Binary Layout

cond

31:28

00111

27:23

22:21

0000

19:16

15:12

imm12

11:0

Format Data Proc

Opcode 0x03E00000

Extension A32 (Base)

Operands

Rd
Destination general-purpose register
Operand2
Flexible second operand (register or shifted register)

Other forms of mvn

mvn Vector Bitwise NOT

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x03E00000	MVN{<c>}{<q>} <Rd>, #<const>	A32	cond \| 00111 \| 11 \| 0 \| 0000 \| Rd \| imm12
0xF06F0000	MVN{<c>}{<q>} <Rd>, #<const>	T32	11110 \| i \| 0 \| 0011 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm8
0x01E00060	MVN{<c>}{<q>} <Rd>, <Rm>, RRX	A32	cond \| 00011 \| 11 \| 0 \| 0000 \| Rd \| 00000 \| 11 \| 0 \| Rm
0x01E00000	MVN{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}	A32	cond \| 00011 \| 11 \| 0 \| 0000 \| Rd \| imm5 \| stype \| 0 \| Rm
0x43C0	MVN<c>{<q>} <Rd>, <Rm>	T32	010000 \| 1111 \| Rm \| Rd
0xEA6F0030	MVN{<c>}{<q>} <Rd>, <Rm>, RRX	T32	1110101 \| 0011 \| 0 \| 1111 \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEA6F0000	MVN<c>.W <Rd>, <Rm>	T32	1110101 \| 0011 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x01E00010	MVN{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>	A32	cond \| 00011 \| 11 \| 0 \| 0000 \| Rd \| Rs \| 0 \| stype \| 1 \| Rm

Description

Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. If the destination register is not the PC, the MVNS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. ARM deprecates any use of these encodings. However, when the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    result = NOT(imm32);
    if d == 15 then          // Can only occur for A32 encoding
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged

mvn