stc

Store Coprocessor (A32)

STC{L}<c> <coproc>, <CRd>, [<Rn>, #+/-<imm>]{!}

Stores coprocessor contents to memory.

Pseudocode Operation

if ConditionPassed(cond) then
  address ← if P then (Rn + (imm8 << 2)) else Rn
  if U then address ← Rn + (imm8 << 2) else address ← Rn - (imm8 << 2)
  [address] ← Coproc_store(CRd)
  if W then Rn ← address

Example

STC p15, c0, [r1, #+/-#16]!

Encoding

Binary Layout
cond
31:28
110
27:25
1
24
U
23
0
22
1
21
0
20
Rn
19:16
0101
15:12
111
11:9
0
8
imm8
7:0
 
Format Coprocessor
Opcode 0x0D205E00
Extension A32 (System)

Operands

  • coproc
    CP Num
  • CRd
    Destination coprocessor register
  • Rn
    First source / base general-purpose register

Related

More in A32 (System)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0D005E00 STC{<c>}{<q>} p14, c5, [<Rn>{, #{+/-}<imm>}] A32 cond | 110 | 1 | U | 0 | 0 | 0 | Rn | 0101 | 111 | 0 | imm8
0x0C205E00 STC{<c>}{<q>} p14, c5, [<Rn>], #{+/-}<imm> A32 cond | 110 | 0 | U | 0 | 1 | 0 | Rn | 0101 | 111 | 0 | imm8
0x0D205E00 STC{<c>}{<q>} p14, c5, [<Rn>, #{+/-}<imm>]! A32 cond | 110 | 1 | U | 0 | 1 | 0 | Rn | 0101 | 111 | 0 | imm8
0x0C805E00 STC{<c>}{<q>} p14, c5, [<Rn>], <option> A32 cond | 110 | 0 | 1 | 0 | 0 | 0 | Rn | 0101 | 111 | 0 | imm8
0xED005E00 STC{<c>}{<q>} p14, c5, [<Rn>{, #{+/-}<imm>}] T32 1110110 | 1 | U | 0 | 0 | 0 | Rn | 0101 | 111 | 0 | imm8
0xEC205E00 STC{<c>}{<q>} p14, c5, [<Rn>], #{+/-}<imm> T32 1110110 | 0 | U | 0 | 1 | 0 | Rn | 0101 | 111 | 0 | imm8
0xED205E00 STC{<c>}{<q>} p14, c5, [<Rn>, #{+/-}<imm>]! T32 1110110 | 1 | U | 0 | 1 | 0 | Rn | 0101 | 111 | 0 | imm8
0xEC805E00 STC{<c>}{<q>} p14, c5, [<Rn>], <option> T32 1110110 | 0 | 1 | 0 | 0 | 0 | Rn | 0101 | 111 | 0 | imm8

Description

Store data to System register calculates an address from a base register value and an immediate offset, and stores a word from the DBGDTRRXint System register to memory. It can use offset, post-indexed, pre-indexed, or unindexed addressing. For information about memory accesses, see Memory accesses. In an implementation that includes EL2, the permitted STC access to DBGDTRRXint can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general Non-secure System register accesses to debug registers. For simplicity, the STC pseudocode does not show this possible trap to Hyp mode.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
    address = if index then offset_addr else R[n];

    // System register read from DBGDTRRXint.
    AArch32.SysRegRead(cp, ThisInstr(), address<31:0>);
    if wback then R[n] = offset_addr;