sha256su1

SHA256 Schedule Update 1 (A32)

SHA256SU1.32 <Qd>, <Qn>, <Qm>

SHA256 schedule update instruction 1.

Details

SHA256 Schedule Update 1 performs the second part of SHA256 message schedule expansion, combining three 128-bit registers to compute new message schedule words. It implements the full sigma_0(W[t-15]) + W[t-7] + sigma_1(W[t-2]) + W[t-16] operation. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.

Pseudocode Operation

Qd ← Qd + (Qn >>> 17) XOR (Qn >>> 19) XOR (Qn >> 10) + (Qm <<< 25) XOR (Qm <<< 14) XOR (Qm >> 6); (applied element-wise to 32-bit values)

Example

SHA256SU1.32 q0, q1, q2

Encoding

Binary Layout
11110011
0
0
0
Vn
Vd
1101
N
Q
M
0
Vm
 
Format Crypto 3-Reg
Opcode 0xF3200C00
Extension Crypto

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E006000 SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S A64 01011110 | 00 | 0 | Rm | 0 | 110 | 00 | Rn | Rd

Description

SHA256 schedule update 1.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand1 = V[d, 128];
bits(128) operand2 = V[n, 128];
bits(128) operand3 = V[m, 128];
bits(128) result;
bits(128) T0 = operand3<31:0>:operand2<127:32>;
bits(64) T1;
bits(32) elt;

T1 = operand3<127:64>;
for e = 0 to 1
    elt = Elem[T1, e, 32];
    elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
    elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
    Elem[result, e, 32] = elt;

T1 = result<63:0>;
for e = 2 to 3
    elt = Elem[T1, e-2, 32];
    elt = ROR(elt, 17) EOR ROR(elt, 19) EOR LSR(elt, 10);
    elt = elt + Elem[operand1, e, 32] + Elem[T0, e, 32];
    Elem[result, e, 32] = elt;

V[d, 128] = result;