vadd
Vector Add Double (VFP)
VADD<c>.F64 <Dd>, <Dn>, <Dm>
Adds two double-precision floating-point values.
Details
Adds two double-precision floating-point values (Dn + Dm) and stores the result in Dd. This VFP instruction operates on 64-bit IEEE 754 double-precision operands. The condition flags (N, Z, C, V) are updated based on the floating-point result according to the FPSCR. Execution is conditional based on the <c> condition code and requires VFP extension support in A32/T32 modes.
Pseudocode Operation
Dd ← Dn + Dm
FPSCR.NZCV ← FP_CC(result)Example
VADD.F64 d0, d1, d2
Encoding
Binary Layout
cond
1110
0
D
11
Vn
Vd
10
11
N
0
M
0
Vm
Operands
-
Dd
Destination 64-bit SIMD/FP register -
Dn
First source 64-bit SIMD/FP register -
Dm
Second source 64-bit SIMD/FP register
Reference (Arm AArch32 ISA)
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0xF2000D00 | VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | A32 | 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm | ||
| 0xF2000D40 | VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | A32 | 1111001 | 0 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm | ||
| 0x0E300900 | VADD{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> | A32 | cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm | ||
| 0x0E300A00 | VADD{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> | A32 | cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm | ||
| 0x0E300B00 | VADD{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> | A32 | cond | 1110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm | ||
| 0xEF000D00 | VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | T32 | 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 0 | Vm | ||
| 0xEF000D40 | VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | T32 | 111 | 0 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 0 | Vm | ||
| 0xEE300900 | VADD{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> | T32 | 11101110 | 0 | D | 11 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm | ||
| 0xEE300A00 | VADD{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> | T32 | 11101110 | 0 | D | 11 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm | ||
| 0xEE300B00 | VADD{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> | T32 | 11101110 | 0 | D | 11 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm | ||
| 0xF2000800 | VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | A32 | 1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm | ||
| 0xF2000840 | VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | A32 | 1111001 | 0 | 0 | D | size | Vn | Vd | 1000 | N | 1 | M | 0 | Vm | ||
| 0xEF000800 | VADD{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> | T32 | 111 | 0 | 11110 | D | size | Vn | Vd | 1000 | N | 0 | M | 0 | Vm | ||
| 0xEF000840 | VADD{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> | T32 | 111 | 0 | 11110 | D | size | Vn | Vd | 1000 | N | 1 | M | 0 | Vm |
Description
Vector Add (floating-point) adds corresponding elements in two vectors, and places the results in the destination vector.
Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.
Operation
if ConditionPassed() then
EncodingSpecificOperations(); CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then // Advanced SIMD instruction
for r = 0 to regs-1
for e = 0 to elements-1
Elem[D[d+r],e,esize] = FPAdd(Elem[D[n+r],e,esize], Elem[D[m+r],e,esize],
StandardFPSCRValue());
else // VFP instruction
case esize of
when 16
S[d] = Zeros(16) : FPAdd(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
when 32
S[d] = FPAdd(S[n], S[m], FPSCR[]);
when 64
D[d] = FPAdd(D[n], D[m], FPSCR[]);