ldpsw

Load Pair of Registers Signed Word

LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]

Loads two words and sign-extends them to 64-bit.

Details

The Load Pair of Registers Signed Word instruction loads two words and sign-extends them to 64-bit.

Pseudocode Operation

Xt1 ← Memory[address]

Example

LDPSW x3, x4, [x1, #16]

Encoding

Binary Layout
01101000
01
0
imm7
Rt2
Rn
Rt1
 
Format Load/Store Pair
Opcode 0x69400000
Extension Base

Operands

  • Xt1
    Target 1
  • Xt2
    Target 2
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value