ldpsw

Load Pair of Registers Signed Word

LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]

Loads two words and sign-extends them to 64-bit.

Details

Loads two consecutive signed 32-bit words from memory and sign-extends each to 64 bits, storing them in Xt1 and Xt2. The memory address is computed from the base register Xn (or SP) plus a scaled 7-bit signed immediate offset (scaled by 4). No condition flags are affected. This is an AArch64-only instruction.

Pseudocode Operation

offset ← imm << 2;
address ← (if Xn == 31 then SP else Xn) + offset;
Xt1 ← SignExtend(Mem[address, 4], 32);
Xt2 ← SignExtend(Mem[address + 4, 4], 32);

Example

LDPSW x3, x4, [x1, #16]

Encoding

Binary Layout
01
101
0
010
1
imm7
Rt2
Rn
Rt
 
Format Load/Store Pair
Opcode 0x69400000
Extension Base

Operands

  • Xt1
    Target 1
  • Xt2
    Target 2
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x68C00000 LDPSW <Xt1>, <Xt2>, [<Xn|SP>], #<imm> A64 01 | 101 | 0 | 001 | 1 | imm7 | Rt2 | Rn | Rt
0x69C00000 LDPSW <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]! A64 01 | 101 | 0 | 011 | 1 | imm7 | Rt2 | Rn | Rt
0x69400000 LDPSW <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] A64 01 | 101 | 0 | 010 | 1 | imm7 | Rt2 | Rn | Rt

Description

Load Pair of Registers Signed Word calculates an address from a base register value and an immediate offset, loads two 32-bit words from memory, sign-extends them, and writes them to two registers. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(64) address2;
bits(32) data1;
bits(32) data2;
boolean privileged = PSTATE.EL != EL0;

AccessDescriptor accdesc = CreateAccDescGPR(MemOp_LOAD, FALSE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

if !postindex then
    address = GenerateAddress(address, offset, accdesc);

address2 = GenerateAddress(address, 4, accdesc);
data1 = Mem[address, 4, accdesc];
data2 = Mem[address2, 4, accdesc];
if rt_unknown then
    data1 = bits(32) UNKNOWN;
    data2 = bits(32) UNKNOWN;
X[t, 64] = SignExtend(data1, 64);
X[t2, 64] = SignExtend(data2, 64);
if wback then
    if wb_unknown then
        address = bits(64) UNKNOWN;
    elsif postindex then
        address = GenerateAddress(address, offset, accdesc);
    if n == 31 then
        SP[] = address;
    else
        X[n, 64] = address;