fcvtzs

Floating-Point Convert to Signed Integer (Zero)

FCVTZS <Wd|Xd>, <Hn|Sn|Dn> {, #<fbits>}

Converts float to signed integer, rounding towards zero (Truncate).

Pseudocode Operation

if source_is_nan then
  result ← 0
else
  if fbits_present then
    result ← round_towards_zero(FP_to_signed_integer(Vn) × 2^fbits)
  else
    result ← round_towards_zero(FP_to_signed_integer(Vn))
Rd ← result

Example

FCVTZS Wd, Dn

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
11
20:19
000
18:16
000000
15:10
Rn
9:5
Rd
4:0
 
Format FP Conversion
Opcode 0x1E380000
Extension Floating Point

Operands

  • Wd|Xd
    Destination general-purpose register (32-bit/64-bit)
  • Hn|Sn|Dn
    First source SIMD&FP register (half, single or double-precision)
  • fbits
    Number of fractional bits

Related

Other forms of fcvtzs

  • fcvtzs SVE Floating-Point Convert to Signed Integer
  • fcvtzs Floating-point Convert to Signed Integer (Round…
  • fcvtzs Vector Floating-Point Convert to Signed Integer

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5F00FC00 FCVTZS <V><d>, <V><n>, #<fbits> A64 01 | 0 | 111110 | immh | immb | 11111 | 1 | Rn | Rd
0x0F00FC00 FCVTZS <Vd>.<T>, <Vn>.<T>, #<fbits> A64 0 | Q | 0 | 011110 | immh | immb | 11111 | 1 | Rn | Rd
0x5EF9B800 FCVTZS <Hd>, <Hn> A64 01 | 0 | 11110 | 1 | 1111001101 | 1 | 10 | Rn | Rd
0x5EA1B800 FCVTZS <V><d>, <V><n> A64 01 | 0 | 11110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd
0x0EF9B800 FCVTZS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | 1111001101 | 1 | 10 | Rn | Rd
0x0EA1B800 FCVTZS <Vd>.<T>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | sz | 100001101 | 1 | 10 | Rn | Rd
0x1ED80000 FCVTZS <Wd>, <Hn>, #<fbits> A64 0 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd
0x9ED80000 FCVTZS <Xd>, <Hn>, #<fbits> A64 1 | 0 | 0 | 11110 | 11 | 0 | 11 | 000 | scale | Rn | Rd
0x1E180000 FCVTZS <Wd>, <Sn>, #<fbits> A64 0 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd
0x9E180000 FCVTZS <Xd>, <Sn>, #<fbits> A64 1 | 0 | 0 | 11110 | 00 | 0 | 11 | 000 | scale | Rn | Rd
0x1E580000 FCVTZS <Wd>, <Dn>, #<fbits> A64 0 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd
0x9E580000 FCVTZS <Xd>, <Dn>, #<fbits> A64 1 | 0 | 0 | 11110 | 01 | 0 | 11 | 000 | scale | Rn | Rd
0x1EF80000 FCVTZS <Wd>, <Hn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd
0x9EF80000 FCVTZS <Xd>, <Hn> A64 1 | 0 | 0 | 11110 | 11 | 1 | 11 | 000 | 000000 | Rn | Rd

Description

Floating-point Convert to Signed integer, rounding toward Zero (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit signed integer using the Round towards Zero rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, FALSE, FPCR, rounding, intsize);
X[d, intsize] = intval;