fmlal
Fused Multiply-Add Long (FP16)
Pseudocode Operation
No pseudocode available.
Encoding
Related
More in Float
Reference
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0F800000 | FMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.H[<index>] | A64 | 0 | Q | 0 | 011111 | 0 | L | M | Rm | 0 | 0 | 00 | H | 0 | Rn | Rd | ||
| 0x0E20EC00 | FMLAL <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb> | A64 | 0 | Q | 0 | 01110 | 0 | 0 | 1 | Rm | 11101 | 1 | Rn | Rd | ||
| 0xC1C00000 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>], <Zn>.B, <Zm>.B[<index>] | A64 | 110000011100 | Zm | i4A | Rv | 0 | i4B | Zn | 0 | i4C | off3 | ||
| 0xC1901030 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B[<index>] | A64 | 110000011001 | Zm | 0 | Rv | 1 | i4h | Zn | 11 | i4l | off2 | ||
| 0xC1909020 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B[<index>] | A64 | 110000011001 | Zm | 1 | Rv | 1 | i4h | Zn | 010 | i4l | off2 | ||
| 0xC1300C00 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>], <Zn>.B, <Zm>.B | A64 | 11 | 0000010011 | Zm | 0 | Rv | 011 | Zn | 0 | 0 | off3 | ||
| 0xC1200804 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, <Zm>.B | A64 | 110000010010 | Zm | 0 | Rv | 010 | Zn | 0 | 0 | 1 | off2 | ||
| 0xC1300804 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, <Zm>.B | A64 | 110000010011 | Zm | 0 | Rv | 010 | Zn | 0 | 0 | 1 | off2 | ||
| 0xC1A00820 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.B-<Zn2>.B }, { <Zm1>.B-<Zm2>.B } | A64 | 11 | 000001101 | Zm | 00 | Rv | 010 | Zn | 10 | 0 | 0 | off2 | ||
| 0xC1A10820 | FMLAL ZA.H[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.B-<Zn4>.B }, { <Zm1>.B-<Zm4>.B } | A64 | 11 | 000001101 | Zm | 010 | Rv | 010 | Zn | 010 | 0 | 0 | off2 | ||
| 0xC1801000 | FMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H[<index>] | A64 | 110000011000 | Zm | i3h | Rv | 1 | i3l | Zn | 0 | 0 | off3 | ||
| 0xC1901000 | FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx2}], { <Zn1>.H-<Zn2>.H }, <Zm>.H[<index>] | A64 | 110000011001 | Zm | 0 | Rv | 1 | i3h | Zn | 0 | 0 | 0 | i3l | off2 | ||
| 0xC1909000 | FMLAL ZA.S[<Wv>, <offs1>:<offs2>{, VGx4}], { <Zn1>.H-<Zn4>.H }, <Zm>.H[<index>] | A64 | 110000011001 | Zm | 1 | Rv | 1 | i3h | Zn | 00 | 0 | 0 | i3l | off2 | ||
| 0xC1200C00 | FMLAL ZA.S[<Wv>, <offs1>:<offs2>], <Zn>.H, <Zm>.H | A64 | 110000010010 | Zm | 0 | Rv | 011 | Zn | 0 | 0 | off3 |
Description
Floating-point fused Multiply-Add Long to accumulator (vector). This instruction multiplies corresponding half-precision floating-point values in the vectors in the two source SIMD&FP registers, and accumulates the product to the corresponding vector element of the destination SIMD&FP register. The instruction does not round the result of the multiply before the accumulation. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped. In Armv8.2 and Armv8.3, this is an OPTIONAL instruction. From Armv8.4 it is mandatory for all implementations to support it.
Operation
CheckFPAdvSIMDEnabled64();
bits(datasize DIV 2) operand1 = Vpart[n, part, datasize DIV 2];
bits(datasize DIV 2) operand2 = Vpart[m, part, datasize DIV 2];
bits(datasize) operand3 = V[d, datasize];
bits(datasize) result;
bits(esize DIV 2) element1;
bits(esize DIV 2) element2;
for e = 0 to elements-1
element1 = Elem[operand1, e, esize DIV 2];
element2 = Elem[operand2, e, esize DIV 2];
if sub_op then element1 = FPNeg(element1, FPCR);
Elem[result, e, esize] = FPMulAddH(Elem[operand3, e, esize], element1, element2, FPCR);
V[d, datasize] = result;