fcvtpu

Floating-Point Convert to Unsigned Integer (Plus Infinity)

FCVTPU <Wd|Xd>, <Hn|Sn|Dn>

Converts float to unsigned integer, rounding towards plus infinity.

Pseudocode Operation

if source_is_nan then
  result ← 0
else
  result ← round_to_plus_infinity(FP_to_unsigned_integer(Vn))
Rd ← result

Example

FCVTPU Wd, Dn

Encoding

Binary Layout

0

31

0

30

0

29

11110

28:24

00

23:22

1

21

01

20:19

001

18:16

000000

15:10

Rn

9:5

Rd

4:0

 

Format FP Conversion

Opcode 0x1E290000

Extension Floating Point

Operands

• Wd|Xd
  Destination general-purpose register (32-bit/64-bit)
• Hn|Sn|Dn
  First source SIMD&FP register (half, single or double-precision)

Related

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x7EF9A800	FCVTPU <Hd>, <Hn>		A64		01 | 1 | 11110 | 1 | 1111001101 | 0 | 10 | Rn | Rd
0x7EA1A800	FCVTPU <V><d>, <V><n>		A64		01 | 1 | 11110 | 1 | sz | 100001101 | 0 | 10 | Rn | Rd
0x2EF9A800	FCVTPU <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 01110 | 1 | 1111001101 | 0 | 10 | Rn | Rd
0x2EA1A800	FCVTPU <Vd>.<T>, <Vn>.<T>		A64		0 | Q | 1 | 01110 | 1 | sz | 100001101 | 0 | 10 | Rn | Rd
0x1EE90000	FCVTPU <Wd>, <Hn>		A64		0 | 0 | 0 | 11110 | 11 | 1 | 01 | 001 | 000000 | Rn | Rd
0x9EE90000	FCVTPU <Xd>, <Hn>		A64		1 | 0 | 0 | 11110 | 11 | 1 | 01 | 001 | 000000 | Rn | Rd
0x1E290000	FCVTPU <Wd>, <Sn>		A64		0 | 0 | 0 | 11110 | 00 | 1 | 01 | 001 | 000000 | Rn | Rd
0x9E290000	FCVTPU <Xd>, <Sn>		A64		1 | 0 | 0 | 11110 | 00 | 1 | 01 | 001 | 000000 | Rn | Rd
0x1E690000	FCVTPU <Wd>, <Dn>		A64		0 | 0 | 0 | 11110 | 01 | 1 | 01 | 001 | 000000 | Rn | Rd
0x9E690000	FCVTPU <Xd>, <Dn>		A64		1 | 0 | 0 | 11110 | 01 | 1 | 01 | 001 | 000000 | Rn | Rd

Description

Floating-point Convert to Unsigned integer, rounding toward Plus infinity (scalar). This instruction converts the floating-point value in the SIMD&FP source register to a 32-bit or 64-bit unsigned integer using the Round towards Plus Infinity rounding mode, and writes the result to the general-purpose destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

bits(decode_fltsize) fltval;
bits(intsize) intval;

fltval = V[n, decode_fltsize];
intval = FPToFixed(fltval, 0, TRUE, FPCR, rounding, intsize);
X[d, intsize] = intval;