fmov
Floating-Point Move (General)
FMOV <Wd|Xd>, <Sn|Dn>
Copies bits between a General-Purpose Register (W/X) and FP Register (S/D).
Pseudocode Operation
Rd ← bits(Vn)Example
FMOV Wd, Sn
Encoding
Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
00
20:19
110
18:16
000000
15:10
Rn
9:5
Rd
4:0
Operands
-
Wd|Xd
Destination general-purpose register (32-bit/64-bit) -
Sn|Dn
First source SIMD&FP register (single or double-precision)
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x0F00FC00 | FMOV <Vd>.<T>, #<imm> | A64 | 0 | Q | 0 | 0111100000 | a | b | c | 1111 | 1 | 1 | d | e | f | g | h | Rd | ||
| 0x0F00F400 | FMOV <Vd>.<T>, #<imm> | A64 | 0 | Q | 0 | 0111100000 | a | b | c | 1111 | 0 | 1 | d | e | f | g | h | Rd | ||
| 0x6F00F400 | FMOV <Vd>.2D, #<imm> | A64 | 0 | 1 | 1 | 0111100000 | a | b | c | 1111 | 0 | 1 | d | e | f | g | h | Rd | ||
| 0x05104000 | FMOV <Zd>.<T>, <Pg>/M, #0.0 | A64 | 00000101 | size | 01 | Pg | 0 | 1 | 0 | 00000000 | Zd | ||
| 0x2538C000 | FMOV <Zd>.<T>, #0.0 | A64 | 00100101 | size | 111 | 0 | 0 | 011 | 0 | 00000000 | Zd | ||
| 0x0510C000 | FMOV <Zd>.<T>, <Pg>/M, #<const> | A64 | 00000101 | size | 01 | Pg | 110 | imm8 | Zd | ||
| 0x2539C000 | FMOV <Zd>.<T>, #<const> | A64 | 00100101 | size | 111 | 0 | 0 | 111 | 0 | imm8 | Zd | ||
| 0x1EE04000 | FMOV <Hd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 10000 | 00 | 10000 | Rn | Rd | ||
| 0x1E204000 | FMOV <Sd>, <Sn> | A64 | 0 | 0 | 0 | 11110 | 00 | 10000 | 00 | 10000 | Rn | Rd | ||
| 0x1E604000 | FMOV <Dd>, <Dn> | A64 | 0 | 0 | 0 | 11110 | 01 | 10000 | 00 | 10000 | Rn | Rd | ||
| 0x1EE60000 | FMOV <Wd>, <Hn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 110 | 000000 | Rn | Rd | ||
| 0x9EE60000 | FMOV <Xd>, <Hn> | A64 | 1 | 0 | 0 | 11110 | 11 | 1 | 00 | 110 | 000000 | Rn | Rd | ||
| 0x1EE70000 | FMOV <Hd>, <Wn> | A64 | 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 111 | 000000 | Rn | Rd | ||
| 0x1E270000 | FMOV <Sd>, <Wn> | A64 | 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 111 | 000000 | Rn | Rd |
Description
Floating-point Move to or from general-purpose register without conversion. This instruction transfers the contents of a SIMD&FP register to a general-purpose register, or the contents of a general-purpose register to a SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.
Operation
if op == FPConvOp_CVT_FtoI_JS then
CheckFPAdvSIMDEnabled64();
else
CheckFPEnabled64();
constant boolean merge = IsMerging(FPCR);
constant integer fltsize = if op == FPConvOp_CVT_ItoF && merge then 128 else decode_fltsize;
bits(fltsize) fltval;
bits(intsize) intval;
case op of
when FPConvOp_CVT_FtoI
fltval = V[n, fltsize];
intval = FPToFixed(fltval, 0, unsigned, FPCR, rounding, intsize);
X[d, intsize] = intval;
when FPConvOp_CVT_ItoF
intval = X[n, intsize];
fltval = if merge then V[d, fltsize] else Zeros(fltsize);
Elem[fltval, 0, decode_fltsize] = FixedToFP(intval, 0, unsigned, FPCR, rounding, decode_fltsize);
V[d, fltsize] = fltval;
when FPConvOp_MOV_FtoI
fltval = Vpart[n, part, fltsize];
intval = ZeroExtend(fltval, intsize);
X[d, intsize] = intval;
when FPConvOp_MOV_ItoF
intval = X[n, intsize];
fltval = intval<fltsize-1:0>;
Vpart[d, part, fltsize] = fltval;
when FPConvOp_CVT_FtoI_JS
bit z;
fltval = V[n, fltsize];
(intval, z) = FPToFixedJS(fltval, FPCR, intsize);
PSTATE.<N,Z,C,V> = '0':z:'00';
X[d, intsize] = intval;