ldumin

Atomic Load-Unsigned Minimum Word

LDUMIN <Ws>, <Wt>, [<Xn|SP>]

Atomic unsigned min to memory.

Pseudocode Operation

address ← Xn
original_value ← [address]
new_value ← UnsignedMin(original_value, Ws)
[address] ← new_value
Wt ← original_value
Memory ordering: Release semantics applied

Example

LDUMIN w6, w3, [x1]

Encoding

Binary Layout
10
31:30
111
29:27
0
26
00
25:24
0
23
0
22
1
21
Rs
20:16
0
15
111
14:12
00
11:10
Rn
9:5
Rt
4:0
 
Format Atomic
Opcode 0xB8207000
Extension LSE (Atomics)

Operands

  • Ws
    Value
  • Wt
    Transfer 32-bit integer register (load/store)
  • Xn
    First source / base 64-bit integer register

Related

More in LSE (Atomics)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xB8207000 LDUMIN <Ws>, <Wt>, [<Xn|SP>] A64 10 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 0 | 111 | 00 | Rn | Rt
0xF8207000 LDUMIN <Xs>, <Xt>, [<Xn|SP>] A64 11 | 111 | 0 | 00 | 0 | 0 | 1 | Rs | 0 | 111 | 00 | Rn | Rt

Description

Atomic unsigned minimum on word or doubleword in memory atomically loads a 32-bit word or 64-bit doubleword from memory, compares it against the value held in a register, and stores the smaller value back to memory, treating the values as unsigned numbers. The value initially loaded from memory is returned in the destination register. For more information about memory ordering semantics, see Load-Acquire, Store-Release. For information about memory accesses, see Load/Store addressing modes.

Operation

bits(64) address;
bits(datasize) value;
bits(datasize) data;

AccessDescriptor accdesc = CreateAccDescAtomicOp(MemAtomicOp_UMIN, acquire, release, tagchecked);

value = X[s, datasize];
if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

bits(datasize) comparevalue = bits(datasize) UNKNOWN;    // Irrelevant when not executing CAS
data = MemAtomic(address, comparevalue, value, accdesc);

if t != 31 then
    X[t, regsize] = ZeroExtend(data, regsize);