fminv

Floating-Point Minimum Reduction (NEON)

FMINV <Sd>, <Vn>.<T>

Finds min float in a vector.

Pseudocode Operation

elements ← VecReduction(Vn, 'min')
Sd ← FPMinReduction(elements)
FPSR.IOC ← FPSRAccum from comparisons

Example

FMINV s0, v1.4s.T

Encoding

Binary Layout
0
31
Q
30
0
29
01110
28:24
1
23
011000
22:17
01111
16:12
10
11:10
Rn
9:5
Rd
4:0
 
Format NEON Reduction
Opcode 0x0EB0F800
Extension NEON (v8.0)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Vn
    First source SIMD/FP vector register

Related

Other forms of fminv

  • fminv SVE Floating-Point Minimum Reduction

More in NEON (v8.0)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB0F800 FMINV <V><d>, <Vn>.<T> A64 0 | Q | 0 | 01110 | 1 | 011000 | 01111 | 10 | Rn | Rd
0x6EB0F800 FMINV S<d>, <Vn>.4S A64 0 | 1 | 1 | 01110 | 1 | 0 | 11000 | 01111 | 10 | Rn | Rd
0x65072000 FMINV <V><d>, <Pg>, <Zn>.<T> A64 01100101 | size | 000 | 11 | 1 | 001 | Pg | Zn | Vd

Description

Floating-point Minimum across Vector. This instruction compares all the vector elements in the source SIMD&FP register, and writes the smallest of the values as a scalar to the destination SIMD&FP register. All the values in this instruction are floating-point values. When FPCR.AH is 0, the behavior is as follows: When FPCR.AH is 1, the behavior is as follows: This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand = V[n, datasize];

V[d, esize] = FPReduce(ReduceOp_FMIN, operand, esize, FPCR);