vmaxnm

Vector Maximum Number

VMAXNM<c>.F32 <Qd>, <Qn>, <Qm>

Returns larger value, handling NaNs per IEEE 754-2008.

Pseudocode Operation

for i = 0 to 3
  if isNaN(Qn[i]) and not isNaN(Qm[i])
    Qd[i] ← Qm[i]
  else if isNaN(Qm[i]) and not isNaN(Qn[i])
    Qd[i] ← Qn[i]
  else
    Qd[i] ← max(Qn[i], Qm[i])

Example

VMAXNM.F32 q0, q1, q2

Encoding

Binary Layout

111111101

31:23

D

22

00

21:20

Vn

19:16

Vd

15:12

10

11:10

10

9:8

N

7

0

6

M

5

0

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xFE800A00

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qn
  First source 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register

Related

Other forms of vmaxnm

• vmaxnm Vector Maximum Number (Double)

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF3000F10	VMAXNM{<q>}.<dt> <Dd>, <Dn>, <Dm>		A32		1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm
0xF3000F50	VMAXNM{<q>}.<dt> <Qd>, <Qn>, <Qm>		A32		1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1111 | N | 1 | M | 1 | Vm
0xFE800900	VMAXNM{<q>}.F16 <Sd>, <Sn>, <Sm>		A32		111111101 | D | 00 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xFE800A00	VMAXNM{<q>}.F32 <Sd>, <Sn>, <Sm>		A32		111111101 | D | 00 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xFE800B00	VMAXNM{<q>}.F64 <Dd>, <Dn>, <Dm>		A32		111111101 | D | 00 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xFF000F10	VMAXNM{<q>}.<dt> <Dd>, <Dn>, <Dm>		T32		111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1111 | N | 0 | M | 1 | Vm
0xFF000F50	VMAXNM{<q>}.<dt> <Qd>, <Qn>, <Qm>		T32		111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1111 | N | 1 | M | 1 | Vm

Description

This instruction determines the floating-point maximum number. It handles NaNs in consistence with the IEEE754-2008 specification. It returns the numerical operand when one operand is numerical and the other is a quiet NaN, but otherwise the result is identical to floating-point VMAX. This instruction is not conditional.

Operation

EncodingSpecificOperations();  CheckAdvSIMDOrVFPEnabled(TRUE, advsimd);
if advsimd then             // Advanced SIMD instruction
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[D[n+r], e, esize]; op2 = Elem[D[m+r], e, esize];
            if maximum then
                Elem[D[d+r], e, esize] = FPMaxNum(op1, op2, StandardFPSCRValue());
            else
                Elem[D[d+r], e, esize] = FPMinNum(op1, op2, StandardFPSCRValue());
else                        // VFP instruction
    case esize of
        when 16
            if maximum then
                S[d] = Zeros(16) : FPMaxNum(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
            else
                S[d] = Zeros(16) : FPMinNum(S[n]<15:0>, S[m]<15:0>, FPSCR[]);
        when 32
            if maximum then
                S[d] = FPMaxNum(S[n], S[m], FPSCR[]);
            else
                S[d] = FPMinNum(S[n], S[m], FPSCR[]);
        when 64
            if maximum then
                D[d] = FPMaxNum(D[n], D[m], FPSCR[]);
            else
                D[d] = FPMinNum(D[n], D[m], FPSCR[]);