frsqrts

Vector Floating-Point Reciprocal Sqrt Step

FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Newton-Raphson step for reciprocal square root refinement.

Details

Computes the Newton-Raphson reciprocal square root refinement step (3.0 - Vn × Vm) / 2.0 for each floating-point element, storing the result in the destination. Operates on 32-bit (sz=0) or 64-bit (sz=1) floating-point elements. This instruction is typically used iteratively with FRSQRTE to converge toward an accurate reciprocal square root. No condition flags are affected. Available in AArch64 NEON.

Pseudocode Operation

if sz == 0 then
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← (3.0 - (Vn[i] * Vm[i])) / 2.0  // 32-bit float
else
  for i = 0 to elements_in_vector - 1:
    Vd[i] ← (3.0 - (Vn[i] * Vm[i])) / 2.0  // 64-bit float

Example

FRSQRTS v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
011101
sz
1
Rm
11111
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0EA0FC00
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5EC03C00 FRSQRTS <Hd>, <Hn>, <Hm> A64 01 | 0 | 11110 | 1 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x5EA0FC00 FRSQRTS <V><d>, <V><n>, <V><m> A64 01 | 0 | 111101 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x0EC03C00 FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 1 | 10 | Rm | 00 | 111 | 1 | Rn | Rd
0x0EA0FC00 FRSQRTS <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 011101 | sz | 1 | Rm | 11111 | 1 | Rn | Rd
0x65001C00 FRSQRTS <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 11 | 1 | Zn | Zd

Description

Floating-point Reciprocal Square Root Step. This instruction multiplies corresponding floating-point values in the vectors of the two source SIMD&FP registers, subtracts each of the products from 3.0, divides these results by 2.0, places the results into a vector, and writes the vector to the destination SIMD&FP register. This instruction can generate a floating-point exception. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

if elements == 1 then
    CheckFPEnabled64();
else
    CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];

bits(esize) element1;
bits(esize) element2;
boolean merge = elements == 1 && IsMerging(FPCR);
bits(128) result = if merge then V[n, 128] else Zeros(128);

for e = 0 to elements-1
    element1 = Elem[operand1, e, esize];
    element2 = Elem[operand2, e, esize];
    Elem[result, e, esize] = FPRSqrtStepFused(element1, element2, FPCR);

V[d, 128] = result;