stnp

Store Pair (Non-temporal)

STNP <Wt1>, <Wt2>, [<Xn|SP>, #<imm>]

Stores two registers, hinting non-temporal data.

Pseudocode Operation

offset ← imm7 << 2
address ← Xn + offset
[address] ← Wt1
[address + 4] ← Wt2

Example

STNP w3, w4, [x1, #16]

Encoding

Binary Layout
00
31:30
101
29:27
0
26
000
25:23
0
22
imm7
21:15
Rt2
14:10
Rn
9:5
Rt
4:0
 
Format Load/Store Pair
Opcode 0x28000000
Extension Base

Operands

  • Wt1
    First transfer 32-bit register (load/store pair)
  • Wt2
    Second transfer 32-bit register (load/store pair)
  • Xn
    First source / base 64-bit integer register
  • imm
    Signed immediate value

Related

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x2C000000 STNP <St1>, <St2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 1 | 000 | 0 | imm7 | Rt2 | Rn | Rt
0x6C000000 STNP <Dt1>, <Dt2>, [<Xn|SP>{, #<imm>}] A64 01 | 101 | 1 | 000 | 0 | imm7 | Rt2 | Rn | Rt
0xAC000000 STNP <Qt1>, <Qt2>, [<Xn|SP>{, #<imm>}] A64 10 | 101 | 1 | 000 | 0 | imm7 | Rt2 | Rn | Rt
0x28000000 STNP <Wt1>, <Wt2>, [<Xn|SP>{, #<imm>}] A64 00 | 101 | 0 | 000 | 0 | imm7 | Rt2 | Rn | Rt
0xA8000000 STNP <Xt1>, <Xt2>, [<Xn|SP>{, #<imm>}] A64 10 | 101 | 0 | 000 | 0 | imm7 | Rt2 | Rn | Rt

Description

Store Pair of Registers, with non-temporal hint, calculates an address from a base register value and an immediate offset, and stores two 32-bit words or two 64-bit doublewords to the calculated address, from two registers. For information about memory accesses, see Load/Store addressing modes. For information about Non-temporal pair instructions, see Load/Store Non-temporal pair.

Operation

bits(64) address;
bits(64) address2;
bits(datasize) data1;
bits(datasize) data2;
constant integer dbytes = datasize DIV 8;
boolean privileged = PSTATE.EL != EL0;

AccessDescriptor accdesc = CreateAccDescGPR(MemOp_STORE, TRUE, privileged, tagchecked);

if n == 31 then
    CheckSPAlignment();
    address = SP[];
else
    address = X[n, 64];

address = GenerateAddress(address, offset, accdesc);

data1 = X[t, datasize];
data2 = X[t2, datasize];
address2 = GenerateAddress(address, dbytes, accdesc);
Mem[address, dbytes, accdesc] = data1;
Mem[address2, dbytes, accdesc] = data2;