saddv

SVE Signed Integer Add Reduction

SADDV <Vd>, <Pg>, <Zn>.<T>

Sums all active signed elements into a scalar result.

Pseudocode Operation

result ← 0
for i = 0 to VL-1
  if Pg[i] == '1' then
    result ← result + SignExtend(Zn[i])
Vd ← result

Example

SADDV v0.4s, p0/m, z1.s.T

Encoding

Binary Layout

00000100

31:24

size

23:22

0000

21:18

0

17

0

16

001

15:13

Pg

12:10

Zn

9:5

Vd

4:0

 

Format SVE Reduction

Opcode 0x04002000

Extension SVE

Operands

• Vd
  Dest Scalar
• Pg
  Mask
• Zn
  Vector

Related

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x04002000	SADDV <Dd>, <Pg>, <Zn>.<T>		A64		00000100 | size | 0000 | 0 | 0 | 001 | Pg | Zn | Vd

Description

Signed add horizontally across all lanes of a vector, and place the result in the SIMD&FP scalar destination register. Narrow elements are first sign-extended to 64 bits. Inactive elements in the source vector are treated as zero.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = Z[n, VL];
integer sum = 0;

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        integer element = SInt(Elem[operand, e, esize]);
        sum = sum + element;

V[d, 64] = sum<63:0>;