not

SVE Bitwise NOT

NOT <Zdn>.<T>, <Pg>/M, <Zdn>.<T>

Inverts bits.

Pseudocode Operation

for e = 0 to VL/getElementSize(T)-1
  if Pg[e] == 1 then
    Zdn[e] ← ~Zdn[e]
  end if
end for

Example

NOT z0.s.T, p0/m/M, z0.s.T

Encoding

Binary Layout

00000100

31:24

size

23:22

011

21:19

18:17

101

15:13

12:10

9:5

4:0

Format SVE Integer Unary

Opcode 0x041EA000

Extension SVE

Operands

Zdn
Dest/Src
Pg
Mask

Other forms of not

not Vector Bitwise NOT

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x2E205800	NOT <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 1 \| 01110 \| 00 \| 10000 \| 00101 \| 10 \| Rn \| Rd
0x25004200	NOT <Pd>.B, <Pg>/Z, <Pn>.B	A64	00100101 \| 0 \| 0 \| 00 \| Pm \| 01 \| Pg \| 1 \| Pn \| 0 \| Pd
0x041EA000	NOT <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	00000100 \| size \| 011 \| 11 \| 0 \| 101 \| Pg \| Zn \| Zd

Description

Bitwise invert each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = NOT element;

Z[d, VL] = result;

not