mov.w

Move (Wide)

MOV.W <Rd>, <Operand2>

Thumb-2 32-bit Move.

Details

Moves Operand2 into Rd without affecting any flags (the S bit is fixed to 0 in this variant). This is a Thumb-2 32-bit instruction that allows encoding of larger immediates (via modified immediate) and access to high registers (R8–R15), providing greater flexibility than 16-bit Thumb MOV.

Pseudocode Operation

Rd ← Operand2;

Example

MOV.W r0, r2

Encoding

Binary Layout

1110101

0010

1111

imm3

imm2

stype

Format Thumb2 Data Proc

Opcode 0xEA4F0000

Extension T32 (Thumb2)

Operands

Rd
Destination general-purpose register
Operand2
Flexible second operand (register or shifted register)

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x03A00000	MOV{<c>}{<q>} <Rd>, #<const>	A32	cond \| 00111 \| 01 \| 0 \| 0000 \| Rd \| imm12
0x2000	MOV<c>{<q>} <Rd>, #<imm8>	T32	001 \| 00 \| Rd \| imm8
0xF04F0000	MOV<c>.W <Rd>, #<const>	T32	11110 \| i \| 0 \| 0010 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm8
0x01A00060	MOV{<c>}{<q>} <Rd>, <Rm>, RRX	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| 00000 \| 11 \| 0 \| Rm
0x01A00000	MOV{<c>}{<q>} <Rd>, <Rm> {, <shift> #<amount>}	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| imm5 \| stype \| 0 \| Rm
0x4600	MOV{<c>}{<q>} <Rd>, <Rm>	T32	010001 \| 10 \| D \| Rm \| Rd
0x0000	MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>}	T32	000 \| op \| imm5 \| Rm \| Rd
0xEA4F0030	MOV{<c>}{<q>} <Rd>, <Rm>, RRX	T32	1110101 \| 0010 \| 0 \| 1111 \| 0 \| 000 \| Rd \| 00 \| 11 \| Rm
0xEA4F0000	MOV{<c>}.W <Rd>, <Rm> {, LSL #0}	T32	1110101 \| 0010 \| 0 \| 1111 \| 0 \| imm3 \| Rd \| imm2 \| stype \| Rm
0x01A00010	MOV{<c>}{<q>} <Rd>, <Rm>, <shift> <Rs>	A32	cond \| 00011 \| 01 \| 0 \| 0000 \| Rd \| Rs \| 0 \| stype \| 1 \| Rm
0x4000	MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs>	T32	010000 \| op \| Rs \| Rdm
0x4000	MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs>	T32	010000 \| op \| Rs \| Rdm
0x4000	MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs>	T32	010000 \| op \| Rs \| Rdm
0x4000	MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs>	T32	010000 \| op \| Rs \| Rdm

Description

Move (register) copies a value from a register to the destination register. If the destination register is not the PC, the MOVS variant of the instruction updates the condition flags based on the result. The field descriptions for <Rd> identify the encodings where the PC is permitted as the destination register. If the destination register is the PC:

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    (shifted, carry) = Shift_C(R[m], shift_t, shift_n, PSTATE.C);
    result = shifted;
    if d == 15 then
        if setflags then
            ALUExceptionReturn(result);
        else
            ALUWritePC(result);
    else
        R[d] = result;
        if setflags then
            PSTATE.N = result<31>;
            PSTATE.Z = IsZeroBit(result);
            PSTATE.C = carry;
            // PSTATE.V unchanged