bfc

Bit Field Clear (Thumb)

BFC <Rd>, #<lsb>, #<width>

Clears a bitfield in a register.

Details

Clears a contiguous bitfield in a register by zeroing bits from lsb to lsb+width-1, leaving other bits unchanged. No condition flags are affected. This is a 32-bit Thumb instruction available in ARMv6T2 and later.

Pseudocode Operation

msb ← lsb + width - 1
mask ← (1 << (msb + 1)) - (1 << lsb)
Rd ← Rd AND NOT mask

Example

BFC r0, #0, #width

Encoding

Binary Layout
11110
0
11
01
1
0
1111
0
imm3
Rd
imm2
0
msb
 
Format Thumb Bitfield
Opcode 0xF36F0000
Extension A32 (Base)

Operands

  • Rd
    Destination general-purpose register
  • lsb
    Start
  • width
    Width

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x07C0001F BFC{<c>}{<q>} <Rd>, #<lsb>, #<width> A32 cond | 0111110 | msb | Rd | lsb | 001 | 1111
0xF36F0000 BFC{<c>}{<q>} <Rd>, #<lsb>, #<width> T32 11110 | 0 | 11 | 01 | 1 | 0 | 1111 | 0 | imm3 | Rd | imm2 | 0 | msb

Description

Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    R[d]<msbit:lsbit> = Replicate('0', (msbit-lsbit)+1);
    // Other bits of R[d] are unchanged