vacge

Vector Absolute Compare Greater or Equal

VACGE<c>.F32 <Qd>, <Qn>, <Qm>

Compares absolute values (|Vn| >= |Vm|).

Details

Vector Absolute Compare Greater or Equal compares the absolute values of corresponding floating-point elements in Qn and Qm, setting each element in Qd to all 1s (true) if |Qn[i]| >= |Qm[i]|, or all 0s (false) otherwise. The comparison is per-element on 32-bit floating-point values. All condition flags (N, Z, C, V) remain unaffected. This is an A32/T32 NEON floating-point instruction.

Pseudocode Operation

for i = 0 to elements-1 do
  if FPAbs(Qn[i]) >= FPAbs(Qm[i]) then
    Qd[i] ← 0xFFFFFFFF
  else
    Qd[i] ← 0x00000000

Example

VACGE.F32 q0, q1, q2

Encoding

Binary Layout
1111001
1
0
D
0
sz
Vn
Vd
1110
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF3000E10
Extension NEON (SIMD)

Operands

  • Qd
    Dest Mask
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3000E10 VACGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 1 | Vm
0xF3000E50 VACGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1110 | N | 1 | M | 1 | Vm
0xFF000E10 VACGE{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1110 | N | 0 | M | 1 | Vm
0xFF000E50 VACGE{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1110 | N | 1 | M | 1 | Vm

Description

Vector Absolute Compare Greater Than or Equal takes the absolute value of each element in a vector, and compares it with the absolute value of the corresponding element of a second vector. If the first is greater than or equal to the second, the corresponding element in the destination vector is set to all ones. Otherwise, it is set to all zeros. The operands and result can be quadword or doubleword vectors. They must all be the same size. The operand vector elements are floating-point numbers. The result vector elements are the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = FPAbs(Elem[D[n+r],e,esize]);  op2 = FPAbs(Elem[D[m+r],e,esize]);
            boolean test_passed;
            if or_equal then
                test_passed = FPCompareGE(op1, op2, StandardFPSCRValue());
            else
                test_passed = FPCompareGT(op1, op2, StandardFPSCRValue());
            Elem[D[d+r],e,esize] = if test_passed then Ones(esize) else Zeros(esize);