smax

Vector Signed Maximum

SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T>

Returns larger signed integer per element.

Details

Computes the signed maximum of corresponding elements from two source vectors and stores the result in the destination vector. The operation processes all elements in parallel; Q determines 64-bit (Q=0) or 128-bit (Q=1) operation, and size determines element width (8, 16, 32, or 64 bits). This is a NEON SIMD instruction available in AArch64 only. No condition flags are affected.

Pseudocode Operation

element_size ← 8 << size;
for i = 0 to (vector_length / element_size - 1)
  Vd.<element_size>[i] ← max_signed(Vn.<element_size>[i], Vm.<element_size>[i]);

Example

SMAX v0.4s.T, v1.4s.T, v2.4s.T

Encoding

Binary Layout
0
Q
0
01110
size
1
Rm
0110
0
1
Rn
Rd
 
Format SIMD Three Register
Opcode 0x0E206400
Extension NEON (SIMD)

Operands

  • Vd
    Destination SIMD/FP vector register
  • Vn
    First source SIMD/FP vector register
  • Vm
    Second source SIMD/FP vector register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E206400 SMAX <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | size | 1 | Rm | 0110 | 0 | 1 | Rn | Rd
0x11C00000 SMAX <Wd>, <Wn>, #<simm> A64 0 | 0 | 0 | 1000111 | 0000 | imm8 | Rn | Rd
0x91C00000 SMAX <Xd>, <Xn>, #<simm> A64 1 | 0 | 0 | 1000111 | 0000 | imm8 | Rn | Rd
0xC120A000 SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101000 | 0000 | 0 | Zdn | 0
0xC120A800 SMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, <Zm>.<T> A64 11000001 | size | 10 | Zm | 101010 | 0000 | 0 | Zdn | 0 | 0
0xC120B000 SMAX { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zdn1>.<T>-<Zdn2>.<T> }, { <Zm1>.<T>-<Zm2>.<T> } A64 11000001 | size | 1 | Zm | 0101100 | 000 | 0 | 0 | Zdn | 0
0xC120B800 SMAX { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zdn1>.<T>-<Zdn4>.<T> }, { <Zm1>.<T>-<Zm4>.<T> } A64 11000001 | size | 1 | Zm | 00101110 | 000 | 0 | 0 | Zdn | 0 | 0
0x1AC06000 SMAX <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 011000 | Rn | Rd
0x9AC06000 SMAX <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 011000 | Rn | Rd
0x04080000 SMAX <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 001 | 0 | 0 | 0 | 000 | Pg | Zm | Zdn
0x2528C000 SMAX <Zdn>.<T>, <Zdn>.<T>, #<imm> A64 00100101 | size | 101 | 00 | 0 | 11 | 0 | imm8 | Zdn

Description

Signed Maximum (vector). This instruction compares corresponding elements in the vectors in the two source SIMD&FP registers, places the larger of each pair of signed integer values into a vector, and writes the vector to the destination SIMD&FP register. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPAdvSIMDEnabled64();
bits(datasize) operand1 = V[n, datasize];
bits(datasize) operand2 = V[m, datasize];
bits(datasize) result;
integer element1;
integer element2;
integer maxmin;

for e = 0 to elements-1
    element1 = Int(Elem[operand1, e, esize], unsigned);
    element2 = Int(Elem[operand2, e, esize], unsigned);
    maxmin = if minimum then Min(element1, element2) else Max(element1, element2);
    Elem[result, e, esize] = maxmin<esize-1:0>;

V[d, datasize] = result;