vsqrt

Vector Square Root (VFP)

VSQRT<c>.F32 <Sd>, <Sm>

Calculates square root.

Details

Vector Square Root (VFP) computes the square root of Sm using IEEE 754 semantics and stores the result in Sd. This unary floating-point operation may raise exceptions for invalid operands (negative inputs) or precision issues, updating FPSCR exception flags but not affecting ARM condition flags. Available in A32/T32 with VFP extension; execution is conditional based on the condition code suffix.

Pseudocode Operation

Sd ← FP_SquareRoot(Sm)
FPSCR ← updated with floating-point exception flags

Example

VSQRT.F32 s0, s2

Encoding

Binary Layout
cond
11101
D
11
0
001
Vd
10
10
1
1
M
0
Vm
 
Format VFP Unary
Opcode 0x0EB10AC0
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Sm
    Second source 32-bit floating-point register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EB109C0 VSQRT{<c>}{<q>}.F16 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0x0EB10AC0 VSQRT{<c>}{<q>}.F32 <Sd>, <Sm> A32 cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0x0EB10BC0 VSQRT{<c>}{<q>}.F64 <Dd>, <Dm> A32 cond | 11101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm
0xEEB109C0 VSQRT{<c>}{<q>}.F16 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 001 | Vd | 10 | 01 | 1 | 1 | M | 0 | Vm
0xEEB10AC0 VSQRT{<c>}{<q>}.F32 <Sd>, <Sm> T32 111011101 | D | 11 | 0 | 001 | Vd | 10 | 10 | 1 | 1 | M | 0 | Vm
0xEEB10BC0 VSQRT{<c>}{<q>}.F64 <Dd>, <Dm> T32 111011101 | D | 11 | 0 | 001 | Vd | 10 | 11 | 1 | 1 | M | 0 | Vm

Description

Square Root calculates the square root of the value in a floating-point register and writes the result to another floating-point register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckVFPEnabled(TRUE);
    case esize of
        when 16 S[d] = Zeros(16) : FPSqrt(S[m]<15:0>, FPSCR[]);
        when 32 S[d] = FPSqrt(S[m], FPSCR[]);
        when 64 D[d] = FPSqrt(D[m], FPSCR[]);