ldapr
Load-Acquire RCpc Register
LDAPR <Wt>, [<Xn|SP>]
Loads a word with RCpc Acquire semantics.
Pseudocode Operation
Wt ← [Xn]; // Load with RCpc acquire semantics; address alignment: 4 bytes
Example
LDAPR w3, [x1]
Encoding
Binary Layout
10
31:30
111
29:27
0
26
00
25:24
1
23
0
22
1
21
11111
20:16
1
15
100
14:12
00
11:10
Rn
9:5
Rt
4:0
Operands
-
Wt
Transfer 32-bit integer register (load/store) -
Xn
First source / base 64-bit integer register
Related
More in Base (RCpc)
Reference
View in Arm A64 ISA Reference ↗
Arm A64 ISA
Instruction Forms
| Encoding | Instruction | ISA | Bit pattern | ||
|---|---|---|---|---|---|
| 0x99C00800 | LDAPR <Wt>, [<Xn|SP>], #4 | A64 | 10 | 0110011 | 1 | 000000000010 | Rn | Rt | ||
| 0xD9C00800 | LDAPR <Xt>, [<Xn|SP>], #8 | A64 | 11 | 0110011 | 1 | 000000000010 | Rn | Rt | ||
| 0xB8BFC000 | LDAPR <Wt>, [<Xn|SP> {, #0}] | A64 | 10 | 111 | 0 | 00 | 1 | 0 | 1 | 11111 | 1 | 100 | 00 | Rn | Rt | ||
| 0xF8BFC000 | LDAPR <Xt>, [<Xn|SP> {, #0}] | A64 | 11 | 111 | 0 | 00 | 1 | 0 | 1 | 11111 | 1 | 100 | 00 | Rn | Rt |
Description
Load-Acquire RCpc Register derives an address from a base register value, loads a 32-bit word or 64-bit doubleword from the derived address in memory, and writes it to a register. The instruction has memory ordering semantics as described in Load-Acquire, Load-AcquirePC, and Store-Release, except that: This difference in memory ordering is not described in the pseudocode. For information about memory accesses, see Load/Store addressing modes.
Operation
bits(64) address;
bits(datasize) data;
constant integer dbytes = datasize DIV 8;
AccessDescriptor accdesc = CreateAccDescLDAcqPC(tagchecked);
if n == 31 then
CheckSPAlignment();
address = SP[];
else
address = X[n, 64];
data = Mem[address, dbytes, accdesc];
X[t, regsize] = ZeroExtend(data, regsize);
if wback then
if wb_unknown then
address = bits(64) UNKNOWN;
else
address = GenerateAddress(address, offset, accdesc);
if n == 31 then
SP[] = address;
else
X[n, 64] = address;