vst1

Vector Store Multiple (Single Element)

VST1<c>.<size> <list>, [<Rn>]{!}

Stores vector data to memory.

Pseudocode Operation

address ← Rn
for each register in list:
  [address] ← register value (element size as specified)
  address ← address + (register_width_in_bytes)
if postindex:
  Rn ← Rn + (total_bytes_stored)

Example

VST1.size {r0-r3}, [r1]!

Encoding

Binary Layout
111101001
31:23
D
22
0
21
0
20
Rn
19:16
Vd
15:12
00
11:10
00
9:8
index_align
7:4
1101
3:0
 
Format NEON Store
Opcode 0xF480000D
Extension NEON (SIMD)

Operands

  • list
    Src Registers
  • Rn
    First source / base general-purpose register

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF480000F VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | 1111
0xF480000D VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | 1101
0xF4800000 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | Rm
0xF480040F VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 00 | index_align | 1111
0xF480040D VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 00 | index_align | 1101
0xF4800400 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 01 | 00 | index_align | Rm
0xF480080F VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 00 | index_align | 1111
0xF480080D VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 00 | index_align | 1101
0xF4800800 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> A32 111101001 | D | 0 | 0 | Rn | Vd | 10 | 00 | index_align | Rm
0xF980000F VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | 1111
0xF980000D VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | 1101
0xF9800000 VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}], <Rm> T32 111110011 | D | 0 | 0 | Rn | Vd | 00 | 00 | index_align | Rm
0xF980040F VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}] T32 111110011 | D | 0 | 0 | Rn | Vd | 01 | 00 | index_align | 1111
0xF980040D VST1{<c>}{<q>}.<size> <list>, [<Rn>{:<align>}]! T32 111110011 | D | 0 | 0 | Rn | Vd | 01 | 00 | index_align | 1101

Description

Store single element from one lane of one register stores one element to memory from one element of a register. For details of the addressing mode, see Advanced SIMD addressing mode. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    CheckAdvSIMDEnabled();

    address = R[n];

    boolean nontemporal = FALSE;
    boolean tagchecked  = FALSE;
    AccessDescriptor accdesc = CreateAccDescASIMD(MemOp_STORE, nontemporal, tagchecked);
    if !IsAligned(address, alignment) then
        AArch32.Abort(address, AlignmentFault(accdesc));

    MemU[address,ebytes] = Elem[D[d],index,8*ebytes];
    if wback then
        if register_index then
            R[n] = R[n] + R[m];
        else
            R[n] = R[n] + ebytes;