vmul

Vector Multiply

VMUL<c>.<dt> <Qd>, <Qn>, <Qm>

Multiplies elements.

Details

Performs element-wise multiplication of two 128-bit SIMD registers, storing results in the destination. The sz field determines 16-bit or 32-bit element width. Condition flags N, Z, C, V are unaffected. This is an A32/T32 NEON instruction with no privilege restrictions.

Pseudocode Operation

for i = 0 to (128 / element_width) - 1:
  Qd[i] ← Qn[i] × Qm[i]

Example

VMUL.dt q0, q1, q2

Encoding

Binary Layout
1111001
op
0
D
size
Vn
Vd
1001
N
0
M
1
Vm
 
Format NEON 3-Reg
Opcode 0xF2000910
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qn
    First source 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3000D10 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xF3000D50 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | 1 | 0 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0x0E200900 VMUL{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0x0E200A00 VMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> A32 cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0x0E200B00 VMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> A32 cond | 1110 | 0 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xFF000D10 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 0 | M | 1 | Vm
0xFF000D50 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | 1 | 11110 | D | 0 | sz | Vn | Vd | 1101 | N | 1 | M | 1 | Vm
0xEE200900 VMUL{<c>}{<q>}.F16 {<Sd>,} <Sn>, <Sm> T32 11101110 | 0 | D | 10 | Vn | Vd | 10 | 01 | N | 0 | M | 0 | Vm
0xEE200A00 VMUL{<c>}{<q>}.F32 {<Sd>,} <Sn>, <Sm> T32 11101110 | 0 | D | 10 | Vn | Vd | 10 | 10 | N | 0 | M | 0 | Vm
0xEE200B00 VMUL{<c>}{<q>}.F64 {<Dd>,} <Dn>, <Dm> T32 11101110 | 0 | D | 10 | Vn | Vd | 10 | 11 | N | 0 | M | 0 | Vm
0xF2000910 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> A32 1111001 | op | 0 | D | size | Vn | Vd | 1001 | N | 0 | M | 1 | Vm
0xF2000950 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> A32 1111001 | op | 0 | D | size | Vn | Vd | 1001 | N | 1 | M | 1 | Vm
0xEF000910 VMUL{<c>}{<q>}.<dt> {<Dd>, }<Dn>, <Dm> T32 111 | op | 11110 | D | size | Vn | Vd | 1001 | N | 0 | M | 1 | Vm
0xEF000950 VMUL{<c>}{<q>}.<dt> {<Qd>, }<Qn>, <Qm> T32 111 | op | 11110 | D | size | Vn | Vd | 1001 | N | 1 | M | 1 | Vm

Description

Vector Multiply multiplies corresponding elements in two vectors. For information about multiplying polynomials, see Polynomial arithmetic over {0, 1}. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information, see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            op1 = Elem[Din[n+r],e,esize];  op1val = Int(op1, unsigned);
            op2 = Elem[Din[m+r],e,esize];  op2val = Int(op2, unsigned);
            bits(2 * esize) product;
            if polynomial then
                product = PolynomialMult(op1,op2);
            else
                product = (op1val*op2val)<2*esize-1:0>;
            if long_destination then
                Elem[Q[d>>1],e,2*esize] = product;
            else
                Elem[D[d+r],e,esize] = product<esize-1:0>;