ucvtf

Unsigned Integer Convert to Floating-Point

UCVTF <Hd|Sd|Dd>, <Wn|Xn> {, #<fbits>}

Converts unsigned integer (GPR) to floating-point.

Pseudocode Operation

uint_val ← ZeroExtend(Rn)
if fbits != 0 then
  fp_val ← ConvertToFP(uint_val / 2^fbits)
else
  fp_val ← ConvertToFP(uint_val)
Vd ← fp_val

Example

UCVTF Dd, Wn

Encoding

Binary Layout
0
31
0
30
0
29
11110
28:24
00
23:22
1
21
00
20:19
011
18:16
000000
15:10
Rn
9:5
Rd
4:0
 
Format FP Conversion
Opcode 0x1E230000
Extension Floating Point

Operands

  • Hd|Sd|Dd
    Destination SIMD&FP register (half, single or double-precision)
  • Wn|Xn
    First source general-purpose register (32-bit/64-bit)

Related

Other forms of ucvtf

  • ucvtf SVE Unsigned Integer Convert to Floating-Point

More in Floating Point

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x7F00E400 UCVTF <V><d>, <V><n>, #<fbits> A64 01 | 1 | 111110 | immh | immb | 11100 | 1 | Rn | Rd
0x2F00E400 UCVTF <Vd>.<T>, <Vn>.<T>, #<fbits> A64 0 | Q | 1 | 011110 | immh | immb | 11100 | 1 | Rn | Rd
0x7E79D800 UCVTF <Hd>, <Hn> A64 01 | 1 | 11110 | 0 | 111100 | 11101 | 10 | Rn | Rd
0x7E21D800 UCVTF <V><d>, <V><n> A64 01 | 1 | 111100 | sz | 10000 | 11101 | 10 | Rn | Rd
0x2E79D800 UCVTF <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 01110 | 0 | 111100 | 11101 | 10 | Rn | Rd
0x2E21D800 UCVTF <Vd>.<T>, <Vn>.<T> A64 0 | Q | 1 | 011100 | sz | 10000 | 11101 | 10 | Rn | Rd
0x1EC30000 UCVTF <Hd>, <Wn>, #<fbits> A64 0 | 0 | 0 | 11110 | 11 | 0 | 00 | 011 | scale | Rn | Rd
0x9EC30000 UCVTF <Hd>, <Xn>, #<fbits> A64 1 | 0 | 0 | 11110 | 11 | 0 | 00 | 011 | scale | Rn | Rd
0x1E030000 UCVTF <Sd>, <Wn>, #<fbits> A64 0 | 0 | 0 | 11110 | 00 | 0 | 00 | 011 | scale | Rn | Rd
0x9E030000 UCVTF <Sd>, <Xn>, #<fbits> A64 1 | 0 | 0 | 11110 | 00 | 0 | 00 | 011 | scale | Rn | Rd
0x1E430000 UCVTF <Dd>, <Wn>, #<fbits> A64 0 | 0 | 0 | 11110 | 01 | 0 | 00 | 011 | scale | Rn | Rd
0x9E430000 UCVTF <Dd>, <Xn>, #<fbits> A64 1 | 0 | 0 | 11110 | 01 | 0 | 00 | 011 | scale | Rn | Rd
0x1EE30000 UCVTF <Hd>, <Wn> A64 0 | 0 | 0 | 11110 | 11 | 1 | 00 | 011 | 000000 | Rn | Rd
0x1E230000 UCVTF <Sd>, <Wn> A64 0 | 0 | 0 | 11110 | 00 | 1 | 00 | 011 | 000000 | Rn | Rd

Description

Unsigned integer Convert to Floating-point (scalar). This instruction converts the unsigned integer value in the general-purpose source register to a floating-point value using the rounding mode that is specified by the FPCR, and writes the result to the SIMD&FP destination register. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

constant boolean merge = IsMerging(FPCR);
constant integer fltsize = if merge then 128 else decode_fltsize;
bits(fltsize) fltval;
bits(intsize) intval;

intval = X[n, intsize];
fltval = if merge then V[d, fltsize] else Zeros(fltsize);
Elem[fltval, 0, decode_fltsize] = FixedToFP(intval, 0, TRUE, FPCR, rounding, decode_fltsize);
V[d, fltsize] = fltval;