vcvtn

Vector Convert to Integer (Nearest Even, Double)

VCVTN<c>.<dt>.F64 <Sd>, <Dm>

Converts double to integer, rounding to nearest even.

Details

Converts a 64-bit double-precision floating-point value to a 32-bit integer, rounding to nearest even (banker's rounding). Executes conditionally in A32 and writes the integer result to a 32-bit floating-point register. No condition flags are affected by this instruction.

Pseudocode Operation

if ConditionPassed() then
  Sd = ConvertToInt(Dm, RoundingMode=RoundToNearestEven)

Example

VCVTN.dt.F64 s0, d2

Encoding

Binary Layout
111111101
D
111
1
01
Vd
10
11
op
1
M
0
Vm
 
Format VFP Convert
Opcode 0xFEBD0B40
Extension VFP (Float)

Operands

  • Sd
    Destination 32-bit floating-point register
  • Dm
    Second source 64-bit SIMD/FP register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0xF3B30100 VCVTN{<q>}.<dt>.<dt2> <Dd>, <Dm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 0 | 01 | op | 0 | M | 0 | Vm
0xF3B30140 VCVTN{<q>}.<dt>.<dt2> <Qd>, <Qm> A32 111100111 | D | 11 | size | 11 | Vd | 0 | 0 | 01 | op | 1 | M | 0 | Vm
0xFFB30100 VCVTN{<q>}.<dt>.<dt2> <Dd>, <Dm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 0 | 01 | op | 0 | M | 0 | Vm
0xFFB30140 VCVTN{<q>}.<dt>.<dt2> <Qd>, <Qm> T32 111111111 | D | 11 | size | 11 | Vd | 0 | 0 | 01 | op | 1 | M | 0 | Vm
0xFEBD0940 VCVTN{<q>}.<dt>.F16 <Sd>, <Sm> A32 111111101 | D | 111 | 1 | 01 | Vd | 10 | 01 | op | 1 | M | 0 | Vm
0xFEBD0A40 VCVTN{<q>}.<dt>.F32 <Sd>, <Sm> A32 111111101 | D | 111 | 1 | 01 | Vd | 10 | 10 | op | 1 | M | 0 | Vm
0xFEBD0B40 VCVTN{<q>}.<dt>.F64 <Sd>, <Dm> A32 111111101 | D | 111 | 1 | 01 | Vd | 10 | 11 | op | 1 | M | 0 | Vm

Description

Convert floating-point to integer with Round to Nearest converts a value in a register from floating-point to a 32-bit integer using the Round to Nearest rounding mode, and places the result in a second register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

EncodingSpecificOperations(); CheckVFPEnabled(TRUE);
case esize of
    when 16
        S[d] = FPToFixed(S[m]<15:0>, 0, unsigned, FPSCR[], rounding, 32);
    when 32
        S[d] = FPToFixed(S[m], 0, unsigned, FPSCR[], rounding, 32);
    when 64
        S[d] = FPToFixed(D[m], 0, unsigned, FPSCR[], rounding, 32);