vshr

Vector Shift Right (Immediate)

VSHR<c>.<dt> <Qd>, <Qm>, #<imm>

Shifts elements right.

Pseudocode Operation

shift_amount ← DecodeImmShift(imm6, sz)  // Decodes imm6 based on element size
for i = 0 to 127 by element_size:
  element ← Qm[i+element_size-1:i]
  if is_signed_type:
    Qd[i+element_size-1:i] ← arithmetic_shift_right(element, shift_amount)
  else:
    Qd[i+element_size-1:i] ← element >> shift_amount

Example

VSHR.dt q0, q2, #16

Encoding

Binary Layout

1111001

31:25

U

24

1

23

D

22

imm6

21:16

Vd

15:12

0000

11:8

L

7

0

6

M

5

1

4

Vm

3:0

 

Format NEON Shift

Opcode 0xF2800010

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register
• imm
  Signed immediate value

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2800010	VSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 0000 | L | 0 | M | 1 | Vm
0xF2800050	VSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		A32		1111001 | U | 1 | D | imm6 | Vd | 0000 | L | 1 | M | 1 | Vm
0xEF800010	VSHR{<c>}{<q>}.<type><size> {<Dd>,} <Dm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 0000 | L | 0 | M | 1 | Vm
0xEF800050	VSHR{<c>}{<q>}.<type><size> {<Qd>,} <Qm>, #<imm>		T32		111 | U | 11111 | D | imm6 | Vd | 0000 | L | 1 | M | 1 | Vm
0xF2200110	VSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0		A32		1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xF2200150	VSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0		A32		1111001 | 0 | 0 | D | 10 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm
0xEF200110	VSHR{<c>}{<q>}.<dt> <Dd>, <Dm>, #0		T32		111 | 0 | 11110 | D | 10 | Vn | Vd | 0001 | N | 0 | M | 1 | Vm
0xEF200150	VSHR{<c>}{<q>}.<dt> <Qd>, <Qm>, #0		T32		111 | 0 | 11110 | D | 10 | Vn | Vd | 0001 | N | 1 | M | 1 | Vm

Description

Vector Shift Right takes each element in a vector, right shifts them by an immediate value, and places the truncated results in the destination vector. For rounded results, see VRSHR. The operand and result elements must be the same size, and can be any one of: Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    for r = 0 to regs-1
        for e = 0 to elements-1
            result = Int(Elem[D[m+r],e,esize], unsigned) >> shift_amount;
            Elem[D[d+r],e,esize] = result<esize-1:0>;