vrshl

Vector Rounding Shift Left

VRSHL<c>.<dt> <Qd>, <Qm>, <Qn>

Shifts left with rounding based on a register value.

Pseudocode Operation

for i = 0 to elements_in_Qd - 1
  shift_amount ← signed(Qn[i])
  if shift_amount >= 0 then
    Qd[i] ← Qm[i] << shift_amount
  else
    if shift_amount <= -element_size then
      Qd[i] ← 0
    else
      rounded ← Qm[i] + (1 << (-shift_amount - 1))
      Qd[i] ← rounded >> (-shift_amount)
    endif
  endif
endfor

Example

VRSHL.dt q0, q2, q1

Encoding

Binary Layout

1111001

31:25

U

24

0

23

D

22

size

21:20

Vn

19:16

Vd

15:12

0101

11:8

N

7

0

6

M

5

0

4

Vm

3:0

 

Format NEON 3-Reg

Opcode 0xF2000500

Extension NEON (SIMD)

Operands

• Qd
  Destination 128-bit SIMD register
• Qm
  Second source 128-bit SIMD register
• Qn
  Shift Reg

Related

More in NEON (SIMD)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0xF2000500	VRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 0 | M | 0 | Vm
0xF2000540	VRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>		A32		1111001 | U | 0 | D | size | Vn | Vd | 0101 | N | 1 | M | 0 | Vm
0xEF000500	VRSHL{<c>}{<q>}.<dt> {<Dd>,} <Dm>, <Dn>		T32		111 | U | 11110 | D | size | Vn | Vd | 0101 | N | 0 | M | 0 | Vm
0xEF000540	VRSHL{<c>}{<q>}.<dt> {<Qd>,} <Qm>, <Qn>		T32		111 | U | 11110 | D | size | Vn | Vd | 0101 | N | 1 | M | 0 | Vm

Description

Vector Rounding Shift Left takes each element in a vector, shifts them by a value from the least significant byte of the corresponding element of a second vector, and places the results in the destination vector. If the shift value is positive, the operation is a left shift. If the shift value is negative, it is a rounding right shift. For a truncating shift, see VSHL. The first operand and result elements are the same data type, and can be any one of: The second operand is always a signed integer of the same size. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the Security state and PE mode in which the instruction is executed, an attempt to execute the instruction might be undefined, or trapped to Hyp mode. For more information see Enabling Advanced SIMD and floating-point support.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();  CheckAdvSIMDEnabled();
    integer result;
    for r = 0 to regs-1
        for e = 0 to elements-1
            integer element = Int(Elem[D[m+r], e, esize], unsigned);
            integer shift = SInt(Elem[D[n+r], e, esize]<7:0>);
            if shift >= 0 then  // left shift
                result = element << shift;
            else                // rounding right shift
                shift = -shift;
                result = (element + (1 << (shift - 1))) >> shift;
            Elem[D[d+r], e, esize] = result<esize-1:0>;