vrshl

Vector Rounding Shift Left

VRSHL<c>.<dt> <Qd>, <Qm>, <Qn>

Shifts left with rounding based on a register value.

Details

The Vector Rounding Shift Left instruction shifts left with rounding based on a register value.

Pseudocode Operation

// Shifts left with rounding based on a register value

Example

VRSHL.dt q0, q2, q1

Encoding

Binary Layout
11110010
0
sz
0
Vn
Vd
0101
N
Q
M
0
Vm
 
Format NEON 3-Reg
Opcode 0xF2000500
Extension NEON (SIMD)

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register
  • Qn
    Shift Reg