smlsld

Signed Multiply Subtract Long Dual

SMLSLD{X}<c> <RdLo>, <RdHi>, <Rn>, <Rm>

Dual multiply subtract + 64-bit accumulate.

Details

The Signed Multiply Subtract Long Dual instruction dual multiply subtract + 64-bit accumulate.

Pseudocode Operation

RdLo ← RdHi - Rn
// Flags affected: N, Z, C, V

Example

SMLSLD r1, r0, r1, r2

Encoding

Binary Layout
cond
01110100
Rn
RdLo
RdHi
0101
Rm
 
Format Multiply
Opcode 0x07400050
Extension A32 (DSP)

Operands

  • RdLo
    Dest Lo
  • RdHi
    Dest Hi
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register