sdiv

Signed Divide

SDIV <Wd>, <Wn>, <Wm>

Divides two signed registers.

Details

Divides the signed 32-bit integer in Wn by the signed 32-bit integer in Wm and places the quotient in Wd. If Wm is zero, the result is zero (no exception is raised). No condition flags are affected. This instruction is available in AArch64, ARMv7 with IDIV extension, and Thumb with IDIV extension.

Pseudocode Operation

if Wm == 0 then
  Wd ← 0
else
  Wd ← SignedDiv(Wn, Wm)
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged

Example

SDIV w0, w1, w2

Encoding

Binary Layout
0
0
0
11010110
Rm
00001
1
Rn
Rd
 
Format Data Processing
Opcode 0x1AC00C00
Extension Base

Operands

  • Wd
    Destination 32-bit integer register
  • Wn
    Dividend
  • Wm
    Divisor

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x1AC00C00 SDIV <Wd>, <Wn>, <Wm> A64 0 | 0 | 0 | 11010110 | Rm | 00001 | 1 | Rn | Rd
0x9AC00C00 SDIV <Xd>, <Xn>, <Xm> A64 1 | 0 | 0 | 11010110 | Rm | 00001 | 1 | Rn | Rd
0x04140000 SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 0101 | 0 | 0 | 000 | Pg | Zm | Zdn

Description

Signed Divide divides a signed integer register value by another signed integer register value, and writes the result to the destination register. The condition flags are not affected.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = X[m, datasize];
integer result;

if IsZero(operand2) then
    result = 0;
else
    result = RoundTowardsZero(Real(Int(operand1, FALSE)) / Real(Int(operand2, FALSE)));

X[d, datasize] = result<datasize-1:0>;