sdiv

Signed Divide

SDIV <Wd>, <Wn>, <Wm>

Divides two signed registers.

Pseudocode Operation

if Wm == 0 then
  Wd ← 0
else
  Wd ← SignedDiv(Wn, Wm)
N ← unchanged
Z ← unchanged
C ← unchanged
V ← unchanged

Example

SDIV w0, w1, w2

Encoding

Binary Layout

0

31

0

30

0

29

11010110

28:21

Rm

20:16

00001

15:11

1

10

Rn

9:5

Rd

4:0

 

Format Data Processing

Opcode 0x1AC00C00

Extension Base

Operands

• Wd
  Destination 32-bit integer register
• Wn
  Dividend
• Wm
  Divisor

Related

Other forms of sdiv

• sdiv SVE Signed Divide
• sdiv Signed Divide (Thumb)
• sdiv Signed Divide (A32)

Across architectures

Integer Divide : how x86, ARM, RISC-V, and PowerISA each do this.

More in Base

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x1AC00C00	SDIV <Wd>, <Wn>, <Wm>		A64		0 | 0 | 0 | 11010110 | Rm | 00001 | 1 | Rn | Rd
0x9AC00C00	SDIV <Xd>, <Xn>, <Xm>		A64		1 | 0 | 0 | 11010110 | Rm | 00001 | 1 | Rn | Rd
0x04140000	SDIV <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>		A64		00000100 | size | 0101 | 0 | 0 | 000 | Pg | Zm | Zdn

Description

Signed Divide divides a signed integer register value by another signed integer register value, and writes the result to the destination register. The condition flags are not affected.

Operation

bits(datasize) operand1 = X[n, datasize];
bits(datasize) operand2 = X[m, datasize];
integer result;

if IsZero(operand2) then
    result = 0;
else
    result = RoundTowardsZero(Real(Int(operand1, FALSE)) / Real(Int(operand2, FALSE)));

X[d, datasize] = result<datasize-1:0>;