sha256su0

SHA256 Schedule Update 0 (A32)

SHA256SU0.32 <Qd>, <Qm>

SHA256 schedule update instruction 0.

Details

SHA256 Schedule Update 0 performs the first part of SHA256 message schedule expansion on four 32-bit words held in a 128-bit SIMD register. It processes the sigma_0 function as part of the SHA256 cryptographic algorithm. No condition flags are modified. This instruction requires the ARM Cryptography Extensions and executes only in A32 (ARM) state.

Pseudocode Operation

W[t] ← (W[t] >>> 7) XOR (W[t] >>> 18) XOR (W[t] >> 3); Qd ← result of applying this transformation to each 32-bit element of Qm

Example

SHA256SU0.32 q0, q2

Encoding

Binary Layout
11110011
1
D
11
10
10
Vd
00100
Q
M
0
Vm
 
Format Crypto 2-Reg
Opcode 0xF3B203C0
Extension Crypto

Operands

  • Qd
    Destination 128-bit SIMD register
  • Qm
    Second source 128-bit SIMD register

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x5E282800 SHA256SU0 <Vd>.4S, <Vn>.4S A64 01011110 | 00 | 10100 | 00010 | 10 | Rn | Rd

Description

SHA256 schedule update 0.

Operation

AArch64.CheckFPAdvSIMDEnabled();

bits(128) operand1 = V[d, 128];
bits(128) operand2 = V[n, 128];
bits(128) result;
bits(128) T = operand2<31:0>:operand1<127:32>;
bits(32) elt;

for e = 0 to 3
    elt = Elem[T, e, 32];
    elt = ROR(elt, 7) EOR ROR(elt, 18) EOR LSR(elt, 3);
    Elem[result, e, 32] = elt + Elem[operand1, e, 32];
V[d, 128] = result;