ldrd

Load Register Dual (Thumb)

LDRD <Rt>, <Rt2>, [<Rn>, #+/-<imm>]

Loads two words from memory (Thumb).

Details

Load two consecutive 32-bit words from memory at address [Rn ± imm] and place them in Rt and Rt2. The immediate offset is scaled by 4 (range ±1020 bytes). No condition flags are affected. This instruction is available in T32 (Thumb) and executes in all privilege levels.

Pseudocode Operation

address ← Rn + (imm8 << 2); Rt ← [address]; Rt2 ← [address + 4]

Example

LDRD r3, r4, [r1, #+/-#16]

Encoding

Binary Layout
cond
000
1
U
1
1
0
Rn
Rt
imm4H
1
10
1
imm4L
 
Format Thumb Load
Opcode 0x016000D0
Extension A32 (Base)

Operands

  • Rt
    Dest 1
  • Rt2
    Dest 2
  • Rn
    First source / base general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x014000D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}] A32 cond | 000 | 1 | U | 1 | 0 | 0 | Rn | Rt | imm4H | 1 | 10 | 1 | imm4L
0x004000D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm> A32 cond | 000 | 0 | U | 1 | 0 | 0 | Rn | Rt | imm4H | 1 | 10 | 1 | imm4L
0x016000D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]! A32 cond | 000 | 1 | U | 1 | 1 | 0 | Rn | Rt | imm4H | 1 | 10 | 1 | imm4L
0xE9500000 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn> {, #{+/-}<imm>}] T32 1110100 | 1 | U | 1 | 0 | 1 | Rn | Rt | Rt2 | imm8
0xE8700000 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], #{+/-}<imm> T32 1110100 | 0 | U | 1 | 1 | 1 | Rn | Rt | Rt2 | imm8
0xE9700000 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, #{+/-}<imm>]! T32 1110100 | 1 | U | 1 | 1 | 1 | Rn | Rt | Rt2 | imm8
0x014F00D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, <label> A32 cond | 000 | 1 | U | 1 | 0 | 0 | 1111 | Rt | imm4H | 1 | 10 | 1 | imm4L
0xE85F0000 LDRD{<c>}{<q>} <Rt>, <Rt2>, <label> T32 1110100 | P | U | 1 | W | 1 | 1111 | Rt | Rt2 | imm8
0x010000D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>] A32 cond | 000 | 1 | U | 0 | 0 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 10 | 1 | Rm
0x000000D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>], {+/-}<Rm> A32 cond | 000 | 0 | U | 0 | 0 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 10 | 1 | Rm
0x012000D0 LDRD{<c>}{<q>} <Rt>, <Rt2>, [<Rn>, {+/-}<Rm>]! A32 cond | 000 | 1 | U | 0 | 1 | 0 | Rn | Rt | 0 | 0 | 0 | 0 | 1 | 10 | 1 | Rm

Description

Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    offset_addr = if add then (R[n] + imm32) else (R[n] - imm32);
    address = if index then offset_addr else R[n];
    if IsAligned(address, 8) then
        data = MemA[address,8];
        if BigEndian(AccessType_GPR)  then
            R[t] = data<63:32>;
            R[t2] = data<31:0>;
        else
            R[t] = data<31:0>;
            R[t2] = data<63:32>;
    else
        R[t] = MemA[address,4];
        R[t2] = MemA[address+4,4];
    if wback then R[n] = offset_addr;