fsub

SVE Floating-Point Subtract

FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Subtracts floating-point elements under predicate.

Pseudocode Operation

for i ← 0 to VL/esize - 1
  if Pg[i] == 1 then
    Zdn[i] ← Zdn[i] - Zm[i]
  else
    Zdn[i] ← Zdn[i]  // unchanged

Example

FSUB z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
01100101
31:24
size
23:22
00
21:20
000
19:17
1
16
100
15:13
Pg
12:10
Zm
9:5
Zdn
4:0
 
Format SVE FP Binary
Opcode 0x65018000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Related

Other forms of fsub

  • fsub Floating-Point Subtract (Scalar)
  • fsub Vector Floating-Point Subtract
  • fsub Floating-Point Subtract (Half-Precision)
  • fsub Floating-point Subtract (Single)
  • fsub Floating-point Subtract (Double)

More in SVE

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0EC01400 FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 1 | 10 | Rm | 00 | 010 | 1 | Rn | Rd
0x0EA0D400 FSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 011101 | sz | 1 | Rm | 11010 | 1 | Rn | Rd
0x1EE03800 FSUB <Hd>, <Hn>, <Hm> A64 0 | 0 | 0 | 11110 | 11 | 1 | Rm | 001 | 1 | 10 | Rn | Rd
0x1E203800 FSUB <Sd>, <Sn>, <Sm> A64 0 | 0 | 0 | 11110 | 00 | 1 | Rm | 001 | 1 | 10 | Rn | Rd
0x1E603800 FSUB <Dd>, <Dn>, <Dm> A64 0 | 0 | 0 | 11110 | 01 | 1 | Rm | 001 | 1 | 10 | Rn | Rd
0x65198000 FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const> A64 01100101 | size | 011 | 00 | 1 | 100 | Pg | 0000 | i1 | Zdn
0x65018000 FSUB <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 01100101 | size | 00 | 000 | 1 | 100 | Pg | Zm | Zdn
0x65000400 FSUB <Zd>.<T>, <Zn>.<T>, <Zm>.<T> A64 01100101 | size | 0 | Zm | 000 | 00 | 1 | Zn | Zd
0xC1A01C08 FSUB ZA.<T>[<Wv>, <offs>{, VGx2}], { <Zm1>.<T>-<Zm2>.<T> } A64 110000011 | sz | 1000000 | Rv | 111 | Zm | 00 | 1 | off3
0xC1A41C08 FSUB ZA.H[<Wv>, <offs>{, VGx2}], { <Zm1>.H-<Zm2>.H } A64 110000011 | 0 | 1001000 | Rv | 111 | Zm | 00 | 1 | off3
0xC1A11C08 FSUB ZA.<T>[<Wv>, <offs>{, VGx4}], { <Zm1>.<T>-<Zm4>.<T> } A64 110000011 | sz | 1000010 | Rv | 111 | Zm | 000 | 1 | off3
0xC1A51C08 FSUB ZA.H[<Wv>, <offs>{, VGx4}], { <Zm1>.H-<Zm4>.H } A64 110000011 | 0 | 1001010 | Rv | 111 | Zm | 000 | 1 | off3

Description

Subtract active floating-point elements of the second source vector from corresponding floating-point elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element2 = Elem[operand2, e, esize];
        Elem[result, e, esize] = FPSub(element1, element2, FPCR);
    else
        Elem[result, e, esize] = element1;

Z[dn, VL] = result;