smulbb

Signed Multiply (Bottom x Bottom)

SMULBB<c> <Rd>, <Rn>, <Rm>

Multiplies bottom 16 bits of Rn and Rm.

Pseudocode Operation

if ConditionPassed() then
  operand1 = SignExtend(Rn[15:0], 32)
  operand2 = SignExtend(Rm[15:0], 32)
  Rd = operand1 * operand2

Example

SMULBB r0, r1, r2

Encoding

Binary Layout

cond

31:28

00010

27:23

11

22:21

0

20

Rd

19:16

0000

15:12

Rm

11:8

1

7

0

6

0

5

0

4

Rn

3:0

 

Format Multiply

Opcode 0x01600080

Extension A32 (DSP)

Operands

• Rd
  Destination general-purpose register
• Rn
  Src 1 (Bot)
• Rm
  Src 2 (Bot)

Related

More in A32 (DSP)

Reference

View in Arm A64 ISA Reference ↗ Arm AArch32 ISA

Instruction Forms

Encoding	Instruction		ISA		Bit pattern
0x01600080	SMULBB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		A32		cond | 00010 | 11 | 0 | Rd | 0000 | Rm | 1 | 0 | 0 | 0 | Rn
0xFB10F000	SMULBB{<c>}{<q>} {<Rd>,} <Rn>, <Rm>		T32		111110110 | 001 | Rn | 1111 | Rd | 00 | 0 | 0 | Rm

Description

Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    operand1 = if n_high then R[n]<31:16> else R[n]<15:0>;
    operand2 = if m_high then R[m]<31:16> else R[m]<15:0>;
    result = SInt(operand1) * SInt(operand2);
    R[d] = result<31:0>;
    // Signed overflow cannot occur