and

SVE Bitwise AND (Predicated)

AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

Bitwise AND of two vectors under predicate.

Details

Performs element-wise bitwise AND between two SVE vector registers under predicate control. Only elements where the corresponding predicate bit is 1 are updated; others are left unchanged. No condition flags are affected. This is an AArch64-only SVE instruction requiring SVE support.

Pseudocode Operation

for i = 0 to VL/esize-1 do
  if Pg[i] then
    Zdn[i*esize +: esize] ← Zdn[i*esize +: esize] AND Zm[i*esize +: esize]
  else
    // element unchanged
endfor

Example

AND z0.s.T, p0/m/M, z0.s.T, z2.s.T

Encoding

Binary Layout
00000100
size
011
01
0
000
Pg
Zm
Zdn
 
Format SVE Logic
Opcode 0x041A0000
Extension SVE

Operands

  • Zdn
    Combined destination/source scalable vector register (SVE)
  • Pg
    Mask
  • Zm
    Second source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x0E201C00 AND <Vd>.<T>, <Vn>.<T>, <Vm>.<T> A64 0 | Q | 0 | 01110 | 00 | 1 | Rm | 00011 | 1 | Rn | Rd
0x12000000 AND <Wd|WSP>, <Wn>, #<imm> A64 0 | 00 | 100100 | 0 | immr | imms | Rn | Rd
0x92000000 AND <Xd|SP>, <Xn>, #<imm> A64 1 | 00 | 100100 | N | immr | imms | Rn | Rd
0x0A000000 AND <Wd>, <Wn>, <Wm>{, <shift> #<amount>} A64 0 | 00 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x8A000000 AND <Xd>, <Xn>, <Xm>{, <shift> #<amount>} A64 1 | 00 | 01010 | shift | 0 | Rm | imm6 | Rn | Rd
0x25004000 AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B A64 00100101 | 0 | 0 | 00 | Pm | 01 | Pg | 0 | Pn | 0 | Pd
0x041A0000 AND <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T> A64 00000100 | size | 011 | 01 | 0 | 000 | Pg | Zm | Zdn
0x05800000 AND <Zdn>.<T>, <Zdn>.<T>, #<const> A64 00000101 | 1 | 0 | 0000 | imm13 | Zdn
0x04203000 AND <Zd>.D, <Zn>.D, <Zm>.D A64 00000100 | 0 | 0 | 1 | Zm | 001100 | Zn | Zd

Description

Bitwise AND active elements of the second source vector with corresponding elements of the first source vector and destructively place the results in the corresponding elements of the first source vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand1 = Z[dn, VL];
bits(VL) operand2 = if AnyActiveElement(mask, esize) then Z[m, VL] else Zeros(VL);
bits(VL) result;

for e = 0 to elements-1
    bits(esize) element1 = Elem[operand1, e, esize];
    bits(esize) element2 = Elem[operand2, e, esize];
    if ActivePredicateElement(mask, e, esize) then
        Elem[result, e, esize] = element1 AND element2;
    else
        Elem[result, e, esize] = Elem[operand1, e, esize];

Z[dn, VL] = result;