ldnf1d

SVE Load Non-Fault Contiguous Doublewords

LDNF1D { <Zt>.D }, <Pg>/Z, [<Xn|SP>]

Loads doublewords without faulting.

Details

The SVE Load Non-Fault Contiguous Doublewords instruction loads doublewords without faulting.

Pseudocode Operation

// Loads doublewords without faulting

Example

LDNF1D p0/m/Z, [x1]

Encoding

Binary Layout
10100100
11
101000
Pg
Rn
Zt
 
Format SVE Load
Opcode 0xA4E80000
Extension SVE

Operands

  • Zt
    Transfer scalable vector register (SVE load/store)
  • Pg
    Predicate
  • Xn
    First source / base 64-bit integer register