revw

SVE Reverse Words in Elements

REVW <Zd>.D, <Pg>/M, <Zn>.D

Reverses words within 64-bit elements.

Details

Reverses the byte order of words (32-bit elements) within 64-bit SVE vector elements, operating under predicate control. No condition flags are affected. This instruction is AArch64-only and available with the SVE extension; it swaps the two 32-bit words in each 64-bit element.

Pseudocode Operation

for i = 0 to VL/64-1
  if Pg[i] then
    Zd[i+1:i] ← {Zn[i+31:i], Zn[i+63:i+32]}
  else
    Zd[i+1:i] ← Zd[i+1:i]

Example

REVW z0.s.D, p0/m/M, z1.s.D

Encoding

Binary Layout
00000101
size
1001
1
0
100
Pg
Zn
Zd
 
Format SVE Permute
Opcode 0x05268000
Extension SVE

Operands

  • Zd
    Destination scalable vector register (SVE)
  • Pg
    Mask
  • Zn
    First source scalable vector register (SVE)

Reference (Arm A64 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x05268000 REVW <Zd>.D, <Pg>/M, <Zn>.D A64 00000101 | size | 1001 | 1 | 0 | 100 | Pg | Zn | Zd

Description

Reverse the order of 8-bit bytes, 16-bit halfwords or 32-bit words within each active element of the source vector, and place the results in the corresponding elements of the destination vector. Inactive elements in the destination vector register remain unmodified.

Operation

CheckSVEEnabled();
constant integer VL = CurrentVL;
constant integer PL = VL DIV 8;
constant integer elements = VL DIV esize;
bits(PL) mask = P[g, PL];
bits(VL) operand = if AnyActiveElement(mask, esize) then Z[n, VL] else Zeros(VL);
bits(VL) result = Z[d, VL];

for e = 0 to elements-1
    if ActivePredicateElement(mask, e, esize) then
        bits(esize) element = Elem[operand, e, esize];
        Elem[result, e, esize] = Reverse(element, swsize);

Z[d, VL] = result;