frintp

Floating-Point Round to Integral (Plus Infinity)

FRINTP <Hd|Sd|Dd>, <Hn|Sn|Dn>

Rounds float to integral value towards plus infinity (Ceil).

Pseudocode Operation

Vd ← RoundTowardsPlusInfinity(Vn)

Example

FRINTP Dd, Dn

Encoding

Binary Layout

11110

28:24

23:22

1001

21:18

001

17:15

10000

14:10

9:5

4:0

Format FP Data Processing

Opcode 0x1E24C000

Extension Floating Point

Operands

Hd|Sd|Dd
Destination SIMD&FP register (half, single or double-precision)
Hn|Sn|Dn
First source SIMD&FP register (half, single or double-precision)

Reference

View in Arm A64 ISA Reference ↗ Arm A64 ISA

Instruction Forms

Encoding	Instruction	ISA	Bit pattern
0x6501A000	FRINTP <Zd>.<T>, <Pg>/M, <Zn>.<T>	A64	01100101 \| size \| 000 \| 00 \| 1 \| 101 \| Pg \| Zn \| Zd
0x0EF98800	FRINTP <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 0 \| 01110 \| 1 \| 1111001100 \| 0 \| 10 \| Rn \| Rd
0x0EA18800	FRINTP <Vd>.<T>, <Vn>.<T>	A64	0 \| Q \| 0 \| 01110 \| 1 \| sz \| 100001100 \| 0 \| 10 \| Rn \| Rd
0x1EE4C000	FRINTP <Hd>, <Hn>	A64	0 \| 0 \| 0 \| 11110 \| 11 \| 1001 \| 001 \| 10000 \| Rn \| Rd
0x1E24C000	FRINTP <Sd>, <Sn>	A64	0 \| 0 \| 0 \| 11110 \| 00 \| 1001 \| 001 \| 10000 \| Rn \| Rd
0x1E64C000	FRINTP <Dd>, <Dn>	A64	0 \| 0 \| 0 \| 11110 \| 01 \| 1001 \| 001 \| 10000 \| Rn \| Rd
0xC1A9E000	FRINTP { <Zd1>.S-<Zd2>.S }, { <Zn1>.S-<Zn2>.S }	A64	11000001 \| 1 \| 0 \| 101 \| 00 \| 1 \| 111000 \| Zn \| 0 \| Zd \| 0
0xC1B9E000	FRINTP { <Zd1>.S-<Zd4>.S }, { <Zn1>.S-<Zn4>.S }	A64	11000001 \| 1 \| 0 \| 111 \| 00 \| 1 \| 111000 \| Zn \| 00 \| Zd \| 00

Description

Floating-point Round to Integral, toward Plus infinity (scalar). This instruction rounds a floating-point value in the SIMD&FP source register to an integral floating-point value of the same size using the Round towards Plus Infinity rounding mode, and writes the result to the SIMD&FP destination register. A zero input gives a zero result with the same sign, an infinite input gives an infinite result with the same sign, and a NaN is propagated as for normal arithmetic. A floating-point exception can be generated by this instruction. Depending on the settings in FPCR, the exception results in either a flag being set in FPSR, or a synchronous exception being generated. For more information, see Floating-point exception traps. Depending on the settings in the CPACR_EL1, CPTR_EL2, and CPTR_EL3 registers, and the current Security state and Exception level, an attempt to execute the instruction might be trapped.

Operation

CheckFPEnabled64();

boolean merge = IsMerging(FPCR);
bits(128) result = if merge then V[d, 128] else Zeros(128);
bits(esize) operand = V[n, esize];

Elem[result, 0, esize] = FPRoundInt(operand, FPCR, rounding, FALSE);

V[d, 128] = result;