uhadd16

Unsigned Halving Add 16

UHADD16<c> <Rd>, <Rn>, <Rm>

Unsigned average of 2 halfwords.

Details

Performs unsigned halving addition of two 16-bit halfwords in parallel, computing the average of each pair. Each halfword of Rn is added to the corresponding halfword of Rm and the result is divided by 2 (rounded down). No condition flags are affected.

Pseudocode Operation

half1_rn ← Rn[15:0]; half2_rn ← Rn[31:16]
half1_rm ← Rm[15:0]; half2_rm ← Rm[31:16]
sum1 ← half1_rn + half1_rm; sum2 ← half2_rn + half2_rm
Rd[15:0] ← sum1 >> 1
Rd[31:16] ← sum2 >> 1

Example

UHADD16 r0, r1, r2

Encoding

Binary Layout
cond
01100
111
Rn
Rd
1
1
1
1
0
00
1
Rm
 
Format SIMD Integer
Opcode 0x06700F10
Extension A32 (DSP)

Operands

  • Rd
    Destination general-purpose register
  • Rn
    First source / base general-purpose register
  • Rm
    Second source / offset general-purpose register

Reference (Arm AArch32 ISA)

Instruction Forms

Encoding Instruction ISA Bit pattern
0x06700F10 UHADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> A32 cond | 01100 | 111 | Rn | Rd | 1 | 1 | 1 | 1 | 0 | 00 | 1 | Rm
0xFA90F060 UHADD16{<c>}{<q>} {<Rd>,} <Rn>, <Rm> T32 111110101 | 001 | Rn | 1111 | Rd | 0 | 1 | 1 | 0 | Rm

Description

Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register.

Operation

if ConditionPassed() then
    EncodingSpecificOperations();
    sum1 = UInt(R[n]<15:0>) + UInt(R[m]<15:0>);
    sum2 = UInt(R[n]<31:16>) + UInt(R[m]<31:16>);
    R[d]<15:0>  = sum1<16:1>;
    R[d]<31:16> = sum2<16:1>;